5 Conformal Jobs

As a Principal Physical Design Engineer at our company, you will play a crucial role in leading a Physical Design team specializing in Low Power Design. Your responsibilities will encompass a wide range of tasks, from performing power analysis at different design stages to developing innovative power optimization techniques. You will be expected to lead and mentor a team, collaborate with cross-functional teams, manage external vendors, and stay updated on the latest advancements in the industry. Your expertise in RTL2GDSII design flow, power analysis and reduction using tools like PrimeTime PX/PrimePower, scripting languages such as TCL and Python, RTL design, and power optimization tools like Power-Artist will be essential. Additionally, your knowledge of low-power architecture, DVFS, memory sleep modes, UPF development, DFT considerations, and low-power verification will be highly valued. Desirable skills include proficiency in tools like FusionCompiler and/or Genus, automating processes using Make systems, Static Timing Analysis using Primetime, and knowledge of tools such as Mentor Calibre, Apache Redhawk, Tessent, Formality, and ICValidator. Strong project management capabilities, excellent communication skills, and the ability to solve complex problems are key attributes we are looking for. At our company, Sondrel, we foster a culture of innovation, collaboration, and personal growth. You will have the opportunity to work on challenging projects, drive technology advancements, and be part of a global team of highly skilled engineers. We offer competitive benefits, a supportive work environment, and opportunities for both domestic and international travel. If you are a proactive individual with a passion for continuous learning and enjoy working in a dynamic environment, we invite you to join our team at Sondrel and contribute to our mission of excellence in SoC design. We are an equal opportunities employer committed to creating an inclusive workplace where diverse perspectives are valued. Your growth and success are important to us, and we are dedicated to providing a fair and supportive environment for all our employees.,

As a Principal Physical Design Engineer at our company, you will play a crucial role in leading a Physical Design team with a focus on Low Power Design. Your expertise in Low Power Design will be utilized as you take the lead in various aspects of the physical design skill set. You will be based in either Hyderabad or Bangalore and will be required to work onsite for 5 days a week. Your responsibilities will include performing comprehensive power analysis from RTL to GDS, contributing to the development and automation of power analysis flows, identifying power inefficiencies, and providing feedback to RTL design. You will be responsible for developing power optimization recipes from RTL to GDS and leading low power aspects of physical design projects. Additionally, you will lead a team to work on customer/internal projects, mentor and develop team members, and coordinate with cross-functional teams to define project requirements. To be successful in this role, you should have at least 10 years of experience in RTL2GDSII design flow, power analysis and reduction using tools like PrimeTime PX/PrimePower, scripting languages such as TCL and Python, and RTL design. Knowledge of low-power architecture, DVFS, memory sleep/LP modes, DFT considerations, and low-power verification is essential. Experience with tools like Power-Artist, UPF development, and low-power physical design is required. You should also have experience in physical design on nodes at 7nm and under, synthesis, placement, CTS, routing, and timing analysis. Desirable skills include knowledge of scripting languages like Perl, advanced knowledge of sub-functions, and experience with tools like Mentor Calibre or Apache Redhawk. Attributes that will help you excel in this role include excellent leadership, communication, negotiation, and time management skills, as well as self-organisation, problem-solving abilities, and self-motivation. At our company, we offer a competitive salary, discretionary annual bonus, transport and meal allowance, 24 days of annual leave, hybrid and flexible working options, and healthcare benefits. We are an equal opportunities employer and value diversity in our team. Join us at Sondrel and be part of a collaborative and innovative environment where you can grow your career and work on cutting-edge technology projects.,

At Cadence, we are committed to hiring and developing leaders and innovators who aspire to create an impact in the technology industry. We are currently seeking a Lead Application Engineer for our GCS team based in Bangalore or Noida. As a pivotal leader in electronic design, Cadence leverages over 30 years of computational software expertise to deliver cutting-edge software, hardware, and IP solutions that bring design concepts to life. Our customers, who are among the most innovative companies worldwide, rely on us to deliver exceptional electronic products across various dynamic market applications. Joining Cadence offers you the opportunity to work with state-of-the-art technology in an environment that fosters creativity, innovation, and impact. Our employee-friendly policies prioritize the well-being and career development of our employees, providing ample opportunities for learning and growth. Our inclusive "One Cadence - One Team" culture celebrates diversity and equity, enabling us to innovate, grow, and succeed with our customers. As a Lead Application Engineer in the GCS Organization for MSA (Multiphysics System Analysis), your role involves collaborating with Cadence customers globally to offer post-sales technical consultation for IC level Power System analysis products. You will work closely with customers to resolve complex issues, help them leverage the latest tools, and guide them in implementing software within their design methodologies. This role allows you to broaden and deepen your technical knowledge, gain exposure to industry best practices, and contribute high-impact knowledge content. Additionally, you will have the opportunity to contribute to the development of key technology solutions and provide feedback to enhance product offerings. You will work in a supportive and flexible environment, where your success is a collective effort and passion for technology and innovation drives us forward. **Job Responsibilities:** - Provide technical support for Voltus product from the Multiphysics System Analysis (MSA) toolset, focusing on productivity and customer satisfaction - Support multiple tools/methods, requiring general domain knowledge and business experience - Assist in creating impactful knowledge content in the MSA domain - Work independently at Cadence or customer facilities to deliver quality results according to schedule requirements - Work on problems of moderate scope that may require analysis of situations, data, or tool problems **Qualifications:** - Bachelors Degree in Electrical/Electronics/Electronics and Communication/VLSI Engineering with 5-7 years of related experience - OR Masters with 3-4 years of related experience - OR PhD with 1 year of related experience **Experience And Technical Skills Required:** - 3-7 years of relevant industry experience in EMIR analysis, PDN analysis with digital signoff tools, and Digital Physical implementation - Strong background in Digital logic Design, CMOS logic Design, Power IR drop analysis, Circuit Design and Analysis, Digital and Behavioral simulation fundamentals - Proficiency in debugging Low power and multiple power domain analysis for chip power integrity sign-off - Understanding of Digital design toolsets of Cadence (Genus/Innovus/Tempus/Conformal) and hardware description languages like VHDL, Verilog, System Verilog - Knowledge of TCL, Perl, or Python scripting **Behavioral Skills Required:** - Strong written, verbal, and presentation skills - Ability to establish a close working relationship with both customer peers and management - Creative problem-solving skills and ability to explore unconventional solutions - Effective collaboration across functions and geographies - Commitment to raising the bar while maintaining integrity Join us at Cadence, where we are dedicated to tackling meaningful challenges and pushing the boundaries of what is possible in technology. Let's solve problems that others can't.,

You are invited to apply for the position of "ASIC RTL Engineer" at Semi Leaf consulting Service located in Bangalore. With 3-8 years of experience, if you are available to join within 30 days and prefer working in a WFO mode, this opportunity might be just for you. As an ASIC RTL Engineer at Semi Leaf, your responsibilities will include working on ASIC RTL design, RTL Logic Synthesis, LEC, Conformal, ECO, FC Check, and having proficiency in either TCL or Python. You must have Synthesis or Implementation experience, familiarity with the Linux environment, excellent communication skills, and experience with at least one serial protocol like UART, I2C, SPI. Skills with SOC Architecture, experience in CDC and Lint, and working on Cortex-M4 core/Sub-system verification/execution environment bring-up are desirable. Additionally, you should be able to develop verification infrastructure for Cortex-M4 Core/Sub-system bring-up, have knowledge of Coresight/Functional Debug architecture, and expertise in UVM/SV knowledge to develop scoreboard/checkers. If you are interested in this opportunity and possess the required experience, kindly share your updated resume with vagdevi@semi-leaf.com. Referrals are also highly appreciated. Join us at Semi Leaf consulting Service and be part of a team of experts dedicated to finding candidates with specialized skills in Semiconductor/VLSI/EDA & Embedded domains.,

The Sr. Staff Physical Design Engineer position at Lattice Semiconductor in Pune, India offers a dynamic opportunity to join the HW design team focused on IP design and full chip integration. As part of a worldwide community of engineers and specialists, you will have the chance to contribute, learn, innovate, and grow within this fast-paced and ambitious organization. Key responsibilities for this role include implementing and leading the RTL to GDSII flow for complex designs, working on various aspects of physical design such as place & route, CTS, routing, floorplanning, powerplanning, timing, and physical signoff. The ideal candidate will have experience in physical design signoff checks, drive efficiency and quality in physical design flow and methodology, collaborate with internal and external teams, and possess scripting knowledge to enhance design efficiency. Additionally, the successful candidate will play a vital role in FPGA design efforts, drive physical design closure of key ASIC blocks & full chip, maintain design quality through quality checks and signoff, develop strong relationships with global teams, mentor colleagues, and may require occasional travel. Requirements for this role include a BS/MS/PhD in Electronics Engineering, Electrical Engineering, Computer Science or equivalent, along with 12+ years of experience in driving physical design activities for ASIC blocks and full chips. Candidates must have multiple tapeout experience and proficiency in industry-standard physical design tools. The ideal candidate should be an independent problem solver, capable of collaborating with diverse groups across different sites and time zones. Lattice Semiconductor values its employees as the cornerstone of its success and offers a comprehensive compensation and benefits program to attract and retain top talent in the industry. As an international developer of low-cost, low-power programmable design solutions, Lattice is committed to customer success and a culture of innovation and achievement. If you thrive in a results-oriented environment, seek individual success within a team-first organization, and are ready to contribute to a collaborative and innovative atmosphere, Lattice Semiconductor may be the perfect fit for you. Feel the energy at Lattice.,