Posted:14 hours ago|
Platform:
On-site
Part Time
THE ROLE:
The AMD IOHUB Team (part of the NBIO organization) is looking for an ASIC Design Engineer to join our growing team. We develop leading-edge I/O connectivity and virtualization technologies powering data center and machine learning workloads. This team is part of the development for tomorrow’s client, server, embedded, graphics, and semi-custom chips. You will be involved in all aspects of IP design starting from architecture to requirements to execution.
As a key contributor to the success of AMD’s IP, you will be part of a leading team to drive and improve AMD’s abilities to deliver the highest quality, industry leading technologies to market. The NBIO Team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.
Key Responsibilities
Complex IP designs including control and datapath.
Understand the functional and performance requirements of the IOHUB within various SOCs
Signoff IP quality for delivery into SOC
Effectively communicate with multi-disciplined teams located across the globe
Preferred Experience
Candidate's Experience - 6+ years
Proven RTL design experience on large ASIC development projects
Strong background working with industry standard synthesis tools, flows and back end timing closure(e.g. Formality, CDC & Linting tools, Design Compiler/FX etc)
Strong background in Verilog and System Verilog
Strong analytical skills and attention to detail
Excellent written and communication skills
Understanding of the IP integration and interactions within an SOC
Must be a self-starter and able to independently drive tasks to completion
Demonstrates the ability to debug issues and quickly identify viable solutions
Team player with proven leadership skills
ACADEMIC CREDENTIALS:
#LI-PM2
Qualifications:
Advanced Micro Devices, Inc
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5.04 - 6.57 Lacs P.A.
5.04 - 6.57 Lacs P.A.
