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SoC RTL Design / SOC Integration - Memory Team

10 - 15 years

0 Lacs

karnataka

Posted:3 weeks ago| Platform: Shine logo

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Skills Required

apb axi ahb ncsim upf asic synthesis timing closure vlsi soc rtl design soc clockreset soc power ipsubsystem bussubsystem peripheralcpu host subsystem flash subsystem digital design principles amba soc bus protocols microarchitecture design dv tools like verdi soc integration gls closure clock domain crossing cdc linting static timing reports analysis formal checking

Work Mode

On-site

Job Type

Full Time

Job Description

Role Overview: You will be responsible for securing an optimal digital IP and circuit by understanding required functions to be developed and designing and verifying them in line with the required goals. Your role will involve contributing in either SoC Clock/reset, SoC Power IP/Subsystem, BUS/Subsystem, Peripheral/CPU, Host Subsystem, or Flash Subsystem based on your prior skills and desire to learn. Key Responsibilities: - Have 10 to 15 years of work experience in VLSI SoC RTL design. - Understand digital design principles, specifically AMBA SoC BUS protocols such as APB, AXI, and AHB. - Create micro-architecture and detailed design documents for SoC design considering performance, power, and area requirements. - Possess strong debugging skills and extensive experience in DV tools like Verdi and NCSIM. - Preferably have SOC integration experience at the Top Level, Block Level, or Subsystem level. - Collaborate with the DV team to enhance verification coverage and work on GLS closure with DV, PD, and Modelling team. - Have knowledge in clock domain crossing (CDC), Linting, UPF, ASIC Synthesis, static timing reports analysis, and Formal checking. - Understand and define constraints, and work on critical high-speed path timing closure in collaboration with back-end teams. Qualification Required: - 10 to 15 years of work experience in VLSI SoC RTL design. - Understanding of AMBA SoC BUS protocols (APB, AXI, AHB). - Strong debugging skills and experience with DV tools like Verdi, NCSIM. - Knowledge of clock domain crossing (CDC), Linting, UPF, ASIC Synthesis, and static timing reports analysis. - Experience in SOC integration at different levels (Top Level, Block Level, Subsystem level). (Note: Additional details about the company were not provided in the job description.),

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