444 Signal Integrity Jobs - Page 17

"> Search Jobs Find Jobs For Where Search Jobs Manager - Signoff products ECO, PrimeClosure Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 10383 Remote Eligible No Date Posted 07/04/2025 We are looking for Manager to join Design Intent testing for our Signoff products E CO, PrimeClosure . This is an exciting opportunity to be part of engineering team to qualify tools with customer flows across the technology working closely with R&D, product engineers, field engineers and customers to solve complex technical challenges in the static timing analysis, design robustness, timing & power modeling, statistical analysis, ECO, extraction, and signal integrity analysis .. Through innovative techniques and ideas, you will help enable customers to accurately validate & use these features on their high-performance designs. Main responsibilities Mentor a team of engineers, set goals for the team, and drive for results. Will drive quality improvement effort by understanding customer design methodologies/flows and validating our tools to meet the required metrics before they are released to the customer. Perform in depth customer incoming root cause analysis to understand the product areas that need improvement and execute proactive testing to reduce customer issues by improving product quality. Identify opportunities to automate and find innovative solutions to improve productivity of teams. Work directly with R&D, Product Engineers, Field Engineers & customers to suggest improvements in Signoff and validation. Use in-depth product understanding to provide technical expertise , diagnose, troubleshoot issues. Key Qualifications The ideal candidate should have domain knowledge in timing, statistical analysis, front-end/back-end semiconductor manufacturing BSEE or equivalent, required with 10-12 years of experience , or MSEE. Synopsys tools like PrimeTime, Siliconsmart, NanoTime, PrimePower and Library Compiler experience is important, PD experience is a bonus. Exceptional debugging skills with good understanding of scripting languages. Experience with mentoring individuals is required. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

Lead the architecture and development of analog/mixed-signal blocks for PCIe 6 and PCIe 7 PHY designs. Ensure designs meet PCIe protocol standards, optimizing for performance, power, and area targets. Oversee the porting of PHY designs to different technology nodes, maintaining signal integrity and performance. Collaborate with cross-functional teams to integrate analog circuits into larger SerDes PHY systems. Develop and implement verification strategies for high-speed analog/mixed-signal circuits using advanced simulation tools. Supervise physical layout to minimize parasitics, device stress, and process variation impacts. Review simulation and measurement data for design validation and compliance with PCIe standards. Provide technical leadership and mentorship to junior engineers in analog/mixed-signal design best practices. Document design features, specifications, test plans, and methodologies for future reference. Collaborate with the characterization team to validate the electrical performance of circuits in silicon. The Impact You Will Have: Drive the development of next-generation PCIe 6 and PCIe 7 PHY designs, contributing to the advancement of high-speed interface technology. Ensure that Synopsys analog/mixed-signal circuits meet stringent industry standards, enhancing the companys reputation for excellence. Facilitate the seamless integration of analog circuits into complex SerDes PHY systems, improving overall system performance. Mentor and develop junior engineers, fostering a culture of continuous learning and innovation within the team. Contribute to the successful porting of PHY designs across different technology nodes, ensuring versatility and adaptability. Enhance the companys design verification processes, leading to more robust and reliable high-speed analog/mixed-signal circuits. What You ll Need: PhD with 5+ years, or MTech/MS with 10+ years of experience in analog/mixed-signal circuit design, with a focus on high-speed interfaces such as PCIe 6/7 or SerDes PHY designs. Extensive experience in transistor-level design of high-speed analog building blocks, such as LDOs, Bandgap references, ADC/DAC, PLLs, DLLs. Proven silicon experience in developing PHY circuits that meet strict PCIe standards. Expertise in high-speed SerDes AFE (Analog Front-End) development, including CTLE and CDR design. Experience designing high-speed SerDes transmitters, with in-depth knowledge of equalization techniques (e.g., DFE, FIR filters, TX pre-emphasis). Strong background in jitter budgeting analysis, including understanding the sources of jitter and strategies for minimizing its impact on signal integrity. Extensive experience with the porting of PHY designs across different technology nodes. Strong expertise in CMOS technologies, including finFET and SOI processes. In-depth understanding of the PCIe protocol, signal integrity requirements, jitter performance, and high-speed clocking. Proven ability to supervise layout design to minimize the effects of parasitics, process variations, and electromigration. Demonstrated ability to lead and mentor design teams, working across departments to ensure successful project outcomes

Leading the development of next-generation DDR/HBM/UCIe IP. Providing guidance and mentorship to team members, ensuring project schedules are met and problems are resolved efficiently. Acting as a project leader, contributing to complex aspects of IP development. Developing and maintaining project schedules, collaborating with cross-functional teams. Designing and verifying CMOS circuits and layouts. Implementing analog mixed-signal simulation strategies and ensuring signal integrity. The Impact You Will Have: Driving the development of cutting-edge IP that powers the future of technology. Enhancing the capabilities of SoCs, enabling faster integration and reduced risk for customers. Contributing to the success of Synopsys by delivering high-quality IP on time. Leading a team of talented engineers, fostering innovation and excellence. Ensuring the highest standards of product quality and efficiency. Playing a key role in the Era of Smart Everything, from AI to IoT. What You ll Need: BTech/MTech degree in a relevant field. 8+ years of experience in analog design. Knowledge of CMOS processes and deep submicron process technologies. Proficiency in CMOS circuit design and layout methodology. Familiarity with analog mixed-signal simulation strategies. Understanding of JEDEC requirements for DDR interfaces and standards. Strong project management and leadership skills. Excellent written and verbal communication skills. Who You Are: A natural leader with the ability to inspire and guide a team. An excellent problem solver with a keen analytical mind. A collaborative team player who thrives in a cross-functional environment. A detail-oriented individual with a commitment to quality and efficiency. A proactive communicator who can convey complex technical information clearly.

Design and develop analog/mixed-signal blocks for PCIe 6 and PCIe 7 PHY designs. Ensure designs meet PCIe protocol standards, optimizing for performance, power, and area targets. Support the porting of PHY designs to different technology nodes, maintaining signal integrity and performance. Collaborate with cross-functional teams to integrate analog circuits into larger SerDes PHY systems. Implement verification strategies for high-speed analog/mixed-signal circuits using advanced simulation tools. Work closely with physical layout teams to minimize parasitics, device stress, and process variation impacts. Analyze simulation and measurement data for design validation and compliance with PCIe standards. Provide technical guidance to junior engineers in analog/mixed-signal design methods. Document design features, specifications, and test plans for future reference. Work with the characterization team to validate the electrical performance of circuits in silicon. The Impact You Will Have: Drive the development of cutting-edge PCIe 6 and PCIe 7 PHY designs, pushing the boundaries of high-speed analog and mixed-signal circuits. Ensure that Synopsys designs meet the highest standards of performance, power efficiency, and area optimization. Enhance the reliability and integrity of our analog circuits as they are ported to new technology nodes. Foster innovation through collaboration with diverse teams, integrating leading-edge analog circuits into sophisticated SerDes PHY systems. Contribute to the verification and validation of high-speed circuits, ensuring compliance with stringent PCIe standards. Mentor and guide junior engineers, nurturing the next generation of top-tier analog designers. What You ll Need: PhD with 3+ years, or MTech/MS with 8+ years of experience in analog/mixed-signal circuit design, with experience in high-speed interfaces such as PCIe or SerDes PHY designs. Strong experience in transistor-level design of high-speed analog building blocks, such as LDOs, Bandgap references, ADC/DAC, PLLs, DLLs. Experience in high-speed SerDes AFE (Analog Front-End) development, including CTLE and CDR design. Experience designing high-speed SerDes transmitters, with knowledge of equalization techniques (e.g., DFE, FIR filters, TX pre-emphasis). Understanding of jitter budgeting analysis, including sources of jitter and strategies for minimizing its impact. Strong knowledge of CMOS technologies, including finFET and GAA processes. Good understanding of the PCIe protocol, signal integrity requirements, and high-speed clocking. Ability to provide input on layout design to minimize the effects of parasitics and process variations. Who You Are: Detail-oriented with a passion for innovation and excellence. Proactive and able to work independently with limited supervision. Strong communicator capable of effectively collaborating with cross-functional teams. Mentor and leader, eager to share knowledge and help develop junior engineers. Results-driven with a focus on delivering high-quality, reliable designs

Developing next-generation high-speed memory interface PHY IPs (DDR/HBM/UCIe) Executing projects in advanced technologies with a focus on analytical and problem-solving skills Designing high-speed IOs for memory interface PHY IP in CMOS/FinFET/GAA Collaborating with cross-functional teams globally to achieve project goals Ensuring product quality and efficiency in all design tasks Staying updated with the latest industry standards and technological advancements The Impact You Will Have: Driving the development of innovative high-speed memory interface PHY IPs Contributing to the integration of advanced capabilities in SoCs Enhancing the performance, power efficiency, and size optimization of target applications Reducing risk and accelerating time-to-market for differentiated products Collaborating with global teams to deliver high-quality products Setting industry benchmarks for advanced analog design technologies What You ll Need: BTech/MTech degree in a relevant field 3+ years of experience in analog design fundamentals and device physics Proficiency in high-speed IO designs in advanced technologies Experience with ESD and reliability concepts Knowledge of JEDEC requirements for memory interfaces and standards Familiarity with signal integrity and/or power integrity is a plus Who You Are: An analytical thinker with strong problem-solving skills A collaborative team player with excellent communication and interpersonal skills Detail-oriented and capable of executing tasks with high precision and efficiency Adaptable and eager to learn new technologies and industry standards Passionate about innovation and technological advancement

Leading the development of next-generation high-speed memory interface IPs (DDR/HBM/UCIe). Driving projects in new technologies with a focus on analytical and problem-solving skills. Acting as a technical mentor to ensure schedules and product quality are met. Developing and maintaining project schedules, working in cross-functional settings. Demonstrating proficiency in design concepts and methodologies. Taking on people management responsibilities, guiding and developing your team. The Impact You Will Have: Contributing to the development of cutting-edge memory interface PHY IPs that drive technological advancements. Ensuring high-quality product development through effective leadership and technical expertise. Mentoring and guiding your team to achieve their full potential and meet project goals. Collaborating with cross-functional teams to drive innovation and efficiency. Maintaining Synopsys leadership position in the semiconductor industry by delivering top-notch IPs. Shaping the future of technology through continuous innovation and excellence. What You ll Need: Bachelor s or Master s degree in Electrical Engineering or related field. 10+ years of experience in analog/mixed signal design. Knowledge of deep submicron process technologies - CMOS/FinFET/GAA. In-depth understanding of JEDEC requirements for memory interfaces and standards. Familiarity with ESD concepts and signal integrity/power integrity is a plus. Proven ability to lead projects and deliver high-quality products efficiently. Excellent written and verbal communication skills. Who You Are: A visionary leader with a passion for analog design and innovation. Analytical and detail-oriented with strong problem-solving skills. An effective communicator and mentor, capable of guiding and developing your team. Proactive and adaptable, able to thrive in cross-functional settings. Committed to delivering high-quality products and driving technological advancements.

Job Overview TE Connectivity s RD/Product Development Engineering Teams conceive original ideas for new products, introduce them into practice. PCB engineer is scalable to contribute individually. He/she is responsible for delivering the project from schematic scratch till the board get fabricated. Stackup analysis, routing strategy, placement feasibility is more important. RD engineer should familiarize in manufacturing process and the different soldering process, IPC standards for SMT PTH library footprint creation. Responsible for all the documentation related to the board design and fabrication data. Typical fields of expertise include Analysing different dielectric materials, knowledge on high-speed design constraint, electrical, software, automation systems, data packaging, testing and measurement, and manufacturing of electrical, mechanical and electronic components, products, and their integration into systems. Responsibilities: TE Connectivity is seeking an experienced candidate for high speed printed circuit board design. The candidate is expected to interface with US and China based engineering teams for input and independently work on printed circuit board layout while also providing guidance and direction to local designers. The position requires that the candidate be able to utilize generalized engineering direction to create detailed custom designs. The candidate will be responsible for ensuring the accuracy and functionality of the end design and be able to take ownership of various aspects of the PCB design. Programs may additionally include pre-layout analysis and coordination of global vendors for prototype fabrication and assembly. Candidate Desired Profile: Candidate should have excellent verbal communication skills, a high attention to detail, be highly motivated, a quick learner, and be able to work independently. Understanding of printed circuit board design, manufacturing, and assembly is required. Experience with printed circuit board design is required. Experience in a senior technical or leadership role is required. Must be able to deliver the board design from scratch schematic to gerber release for manufacturing. Very good exposure in design software - Altium, Allegro, AutoCAD is must. Previous work experience in high-speed board designs will be highly preferred. Altium/Allegro tool scripting knowledge will be an added advantage for this role. Able to address supplier Engineering Queries. Familiarity with the following a plus: CAM350 High speed and/or RF circuits Signal integrity analysis Connectors and cable assemblies PCB manufacturing tolerances and cost drivers PDMLink process ECR/ECN release process Competencies Values: Integrity, Accountability, Inclusion, Innovation, Teamwork ABOUT TE CONNECTIVITY TE Connectivity is a global industrial technology leader creating a safer, sustainable, productive, and connected future. Our broad range of connectivity and sensor solutions enable the distribution of power, signal and data to advance next-generation transportation, renewable energy, automated factories, data centers, medical technology and more. With more than 85, 000 employees, including 8, 000 engineers, working alongside customers in approximately 140 countries. TE ensures that EVERY CONNECTION COUNTS. Learn more at www. te. com and on LinkedIn , Facebook , WeChat, Instagram and X (formerly Twitter). WHAT TE CONNECTIVITY OFFERS: We are pleased to offer you an exciting total package that can also be flexibly adapted to changing life situations - the well-being of our employees is our top priority! Competitive Salary Package Performance-Based Bonus Plans Health and Wellness Incentives Employee Stock Purchase Program Community Outreach Programs / Charity Events Employee Resource Group Across our global sites and business units, we put together packages of benefits that are either supported by TE itself or provided by external service providers. In principle, the benefits offered can vary from site to site. Location:

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Design For Testability - DFT.Experience: 3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Board Design. Experience: 3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: VLSI Physical Verification. Experience1-3 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Board Design. Experience: 3-5 Years.

Lead signal integrity (SI) &power integrity (PI) analysis and simulation for Molex’s high-speed interconnect products,including PCB-mounted connectors, cable systems, optical modules Develop advanced simulation models & methodologies for products NPD Required Candidate profile Exp in signal integrity & power integrity engineering, with a focus on high-speed interconnect systems. Expertise in electromagnetic theory, transmission line theory,high-speed PCB design principles

Hands on experience in Circuit Design implementation of IPs including LDOs, Band Gap reference, Good working knowledgein Current Generators, POR, ADC/DACs, PLLs, Oscillators, Good working knowledge in General Purpose IOs, Temperature sensor, SERDES, PHYs, Good in Die to Die interconnect, High-speed IOs,

About The Role Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client ? Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project ? Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt ? ? Mandatory Skills: ASIC Design. Experience3-5 Years. Reinvent your world. We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention. Come to Wipro. Realize your ambitions. Applications from people with disabilities are explicitly welcome.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Deliver No. Performance Parameter Measure 1. Verification Timeliness Quality of Code/ Number of defects Customer responsiveness Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt Mandatory Skills: VLSI Design For Testability - DFT. Experience3-5 Years.

Position: PCB Designer Location: Navi Mumbai Reporting to: Head -Design & Development Role: Design and develop PCB layouts from schematics, ensuring signal integrity, power efficiency, manufacturability, and compliance with standards. Key Responsibilities: Create schematics, PCB layouts, and libraries using EDA tools. Select components with cost, performance, and availability in mind. Conduct design reviews, simulations, and validations. Collaborate with hardware, procurement, and manufacturing teams. Support prototyping, troubleshoot issues, and ensure compliance. Stay updated on PCB design tools and technology trends. Requirements: Diploma/Bachelors in Electronics, E&TC, or related field. Experience with Altium Designer or similar tools. Strong knowledge of PCB design principles, signal integrity, and thermal management. Good communication and teamwork skills.

Job Overview As a Staff Product Development Engineer in the Signal Integrity Center of Excellence (SI COE), you will lead advanced signal integrity (SI) research, modeling, and validation for next-generation high-speed interconnects used in AI data centers, and high-performance computing (HPC). Your role involves independently conducting SI studies and design platforming, including geometry analysis and simulation-driven optimizations. You will be responsible for exploring new SI methodologies, conducting literature reviews, formulating research plans, programming, simulating, and testing to develop innovative solutionseven in ambiguous environments. You will collaborate closely with mechanical, manufacturing, materials, and operations teams to drive the adoption of cutting-edge SI technologies. As a subject matter expert, you will oversee the entire SI lifecycle, from initial analysis and modeling to design, simulation, prototype fabrication, and final validation. You will tackle complex design challenges, leveraging advanced simulation tools to optimize designs for manufacturability and performance Responsibilities Drive SI design, simulation, and validation for next-gen high-speed interconnects (112G/224G PAM4, PCIe Gen6/7, Co-Packaged, and Near Package) through the product development cycle. Conducting SI COE analysis, including Performing signal integrity simulations and analysis for high-speed interconnect product development. This includes determining the correct simulation methodology and setup to use, as well as a good understanding of the criteria for each interface. Modeling the connector with the consideration of manufacture impact and application impact. Providing solutions to the SI challenges. This includes identifying the problems, making research plans, developing new technologies, and training and sharing the findings with the SI community. Develop novel interconnect solutions by optimizing mating interfaces, lead frames, and PCB transitions for resonance-free, low-loss performance. Enhance bulk cable design & termination techniques to minimize skew, impedance mismatches, and signal degradation. Advance high-frequency testing methodologies beyond 67 GHz with innovative non-PCB-based test fixtures. Utilize AI & big data analytics for predictive SI modeling, auto-routing, and performance optimization. Optimize material selection & electromagnetic design to improve noise isolation, signal integrity, and high-frequency response. Collaborate with NPD teams & industry partners to influence SI strategies, technology roadmaps, and next-gen product designs. Represent TE at industry forums (IEEE, OIF, PCI-SIG, etc.) and contribute to next-gen SI standards. What your background should look like Skills, Experience and Education Bachelors degree in Electrical Engineering or equivalent amount of experience. Minimum of 8+ years of work experience in a signal integrity engineering role. Minimum of 6+ years of work experience in connector development - Experience with interconnect design or experience with connector &/or cable/cable assembly design (high-speed twinax cables, direct attach copper (DAC) cables) Demonstrated experience using Signal integrity analysis tools (Agilent ADS, Ansys HFSS or equivalent, 3D modeling tools) and testing equipment (including VNA, TDR, and BERT). A solid understanding of statistical analysis and AI training. A solid understanding of electromagnetic theory and electrical circuit behavior Strong analytical capabilities to interpret simulation and lab data to identify issues and provide solutions to fix identified problems. Strong understanding of printed circuit board design, fabrication, and assembly. Familiar with material, manufacturing process, and manufacture inspection. Familiar with at least one programming language, such as Matlab, Python, C++, VB, etc Excellent presentation, verbal, and written communication skills with an ability to clearly communicate technical concepts to diverse audiences Ability to work in a global environment – able to accommodate varying time zones, fluent in English (verbal/written), able to collaborate with individuals across geographies The individual must be highly motivated, a quick learner, and able to work independently Nice to have Skills/ Experience Doctor’s degree a PLUS Printed circuit board design (proficient in Altium a PLUS), fabrication and assembly (AutoCAD) Signal conditioning techniques (equalization, amplification) Six Sigma methodologies or other strong data analytics background a PLUS. Experience in project leadership, especially as it applies to design, development & manufacturing teams Direct customer design and support experience Design experience with data center compute equipment like servers, switches, routers, storage, antenna, RF front end, or similar systems.

•Electrical Fundamentals: Strong knowledge of electrical systems and circuits. •On-Site Device Configuration and Wiring: Ability to configure and wire devices accurately. •Programming Skills: Basic proficiency in C, C++, and JavaScript.

Job Overview TE Connectivitys R&D/Product Development Engineering Teams conceive original ideas for new products, introduce them into practice. PCB engineer is scalable to contribute individually. He/she is responsible for delivering the project from schematic scratch till the board get fabricated. Stackup analysis, routing strategy, placement feasibility is more important. R&D engineer should familiarize in manufacturing process and the different soldering process, IPC standards for SMT & PTH library footprint creation. Responsible for all the documentation related to the board design and fabrication data. Typical fields of expertise include Analysing different dielectric materials, knowledge on high-speed design constraint, electrical, software, automation systems, data packaging, testing and measurement, and manufacturing of electrical, mechanical and electronic components, products, and their integration into systems. Responsibilities: TE Connectivity is seeking an experienced candidate for high speed printed circuit board design. The candidate is expected to interface with US and China based engineering teams for input and independently work on printed circuit board layout while also providing guidance and direction to local designers. The position requires that the candidate be able to utilize generalized engineering direction to create detailed custom designs. The candidate will be responsible for ensuring the accuracy and functionality of the end design and be able to take ownership of various aspects of the PCB design. Programs may additionally include pre-layout analysis and coordination of global vendors for prototype fabrication and assembly. Candidate Desired Profile: Qualifications: Candidate should have excellent verbal communication skills, a high attention to detail, be highly motivated, a quick learner, and be able to work independently. Understanding of printed circuit board design, manufacturing, and assembly is required. Experience with printed circuit board design is required. Experience in a senior technical or leadership role is required. Must be able to deliver the board design from scratch schematic to gerber release for manufacturing. Very good exposure in design software - Altium, Allegro, AutoCAD is must. Previous work experience in high-speed board designs will be highly preferred. Altium/Allegro tool scripting knowledge will be an added advantage for this role. Able to address supplier Engineering Queries. Education MTech/PHD Familiarity with the following a plus: CAM350 High speed and/or RF circuits Signal integrity analysis Connectors and cable assemblies PCB manufacturing tolerances and cost drivers PDMLink process ECR/ECN release process What your background should look like Generally requires Bachelors degree in appropriate field with a minimum of 5 years of progressively responsible professional level experience; Masters degree or higher or local equivalent may be preferred at this level

Engineering in ECE or ETC,PCB design using Altium Design Software. Experience in Multi-Layer PCB design,Experience in PCB design with Signal Integrity. Power Integrity and EMI/EMC considerations. Experience in working with Serial protocols such as RS422/485, I2C, SPI, UART etc. Experience in working with Wi-Fi, LoRa and Bluetooth related hardware and antenna selection. Experience in working with Micro controller & Computer Module. Exp in Preparing FEMCA & DFMEA analysis for hardware Design

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.Responsibilities: STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs. Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus. Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation. Evaluate multiple timing methodologies/tools on different designs and technology nodes. Work on automation scripts within STA/PD tools for methodology development. Good Technical writing and Communication skills, should be willing to work in cross-collaborative environment Experience in design automation using TCL/Perl/Python. Familiar with digital flow design implementation RTL to GDS : ICC, Innovous , PT/Tempus Familiar with process technology enablement: Circuit simulations using Hspice/FineSim, Monte Carlo. Education : B.Tech or MTech/MS in Electrical/Electronics/Microelectronics/VLSI. Preferred Qualification/Skills 5 - 10 years of experience in STA/Timing Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling Hands-on experience with STA tools - Prime-time, Tempus Have experience in driving timing convergence at Chip-level and Hard-Macro level In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling, Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus) Knowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation. Proficient is scripting languages TCL, Perl, Awk Basic knowledge of device physics

Required skills: He/She should be able to do top-level floor planning, PG Planning, partitioning,placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. He/She should have worked on 65nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. Provide technical guidance, mentoring to physical design engrs. Interface with front-end ASIC teams to resolve issues. Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques. Timing closure on DDR2/DDR3/PCIE interfaces. Excellent communication skills. Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure. Extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools. Expertise in scripting languages such as PERL, TCL. Strong Physical Verification skill set. Static Timing Analysis in Primetime or Primetime-SI. Good written and oral communication skills. Ability to clearly document plans. Ability to interface with different teams and prioritize work based on project needs.

Roles & Responsibilities: HW Requirement analysis Hardware design, development and debugging Hardware board bring-up and Design validation testing Must have worked in a design environment for complete Hardware development life cycle (HDLC). Must be able to understand & document design requirements at module level & functional level. Good knowledge of Analog, digital and mixed circuit design. Good knowledge of component selection (passives, microprocessor, micro controller, PMIC, Op Amp etc.) Hands on experience on any Schematic and layout design tool like OrCAD, Altium etc. Hands on experience on PSPICE tools like TINA, OrCAD, LTspice Good knowledge of EMI/EMC testing. Must be able to handle BOM stock, online ordering & communicate with vendors for pricing & delivery. Good knowledge of PCB design, Multilayer PCB Design (8-10 Layer) and EMI/EMC compliant PCB layout Basic knowledge of signal integrity, power integrity and High-Speed.

Role Description: Welcoming customers and educating them on the product and the EMI. Educate the customer on the consequences of non-payment Educating and convincing the customer for ECS & NACH ACCEPTANCE if not done Giving customers detailed account directions. Attributes we are looking for A graduate with minimum 6 months experience in tele calling inbound or outbound with fluency in English and Tamil would be an added advantage. Computer literate.

Job Title Embedded Hardware Design Designation: Sr. Engr / Asst Manager Embedded Hardware Design Location: Chennai or Bangalore Experience: 8-12 Years Job Summary (Areas of Responsibility) • Design and Development of Embedded systems required for Actuation Products Lead and execute strategically important NPI and R&D projects Create Technical Product specification and Hardware Software Interface specification (HSI) Design Verification, Testing and validation Test Rigs and Test equipment design and development PCB Design and Layout EMI/EMC Testing and Certification coordination Work closely with the Firmware and Mechanical teams for product integration Work with the Global Engineering teams to ensure quality of deliverables Create and maintain project schedules and timelines Comply with the companys design and development process Core Competencies Experience in designing microcontroller boards and associated peripheral circuits Experience in analogue and digital circuit design, power supply design (LDO, Buck, Boost, Flyback) Experience in actuator and motor control circuit design Experience in high voltage PCB designs and isolation requirements Experience in designing interface circuits and different types of analog and digital sensors. Knowledge of communication interfaces like SPI, I2C, UART, USB, Ethernet, T1L, RS-232/485 Knowledge of Industrial protocols like MODBUS, Profibus, HART, Wireless Hart, etc. Knowledge of Wireless technologies Bluetooth, Wi-Fi , sub-GHz etc., Good understanding of firmware development, firmware architecture, and ability to understand the C/C++ codes. Hands on Experience with ECAD design tools (Mentor Graphics, Altium) for schematic capture and PCB layout design and simulation. Knowledge of component selections, BOM preparation, Power loss estimation/calculation, Thermal dissipation and analysis. Good knowledge on Circuit Simulations, Signal integrity (SI) and Power Integrity (PI) Understanding of EMI/EMC issues, experience with debugging and meet the requirements. Good experience on various industrial product standards, EMI-EMC standards, certification requirements and test procedures. Experience with Reliability analysis, FMEA and MTBF. Good understanding on PCBA and product manufacturing process. DFA, DFT, DFM analysis. Experience in preparing documents like HDD, layout guidelines, test plan, test reports etc., Experience in board bring-up, testing and troubleshooting the electronic circuits. Experience in using equipments like DSO, signal generator, thermal imager, data logger. Experience in system level testing and validation of electronic products. Experience in end-to-end electronic product development Key Skills & Relevant Experience Skills • Good verbal and written communication skills Great attention to detail and problem-solving ability Team Player able to work with others easily Disciplined work ethic Ability to lead a team Experience • Experience in embedded hardware design, development and testing • Some exposure to industrial Actuators design is preferred • Exposure to working in a Global environment will be added advantage • Hands-on experience in EMI/EMC testing / handling