444 Signal Integrity Jobs - Page 18

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Design For Testability - DFT. Experience: 1-3 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: Analog Circuit design. Experience: 3-5 Years.

Role Description: This is a full-time on-site role for a Senior Lead Physical Design Engineer based in Hyderabad. The Senior Physical Design Engineer will be responsible for tasks related to physical design, physical verification, logic design, circuit design, and RTL design in the development of silicon products. Qualifications: He/She should be able to do block level PNR including PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. Minimum of 7-15 years of experience in physical design. He/She should have worked on 7nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. Provide technical guidance, mentoring to physical design engineers. Lead a team of Physical design engineers and be responsible for their blocks closure Interface with front-end ASIC teams to resolve issues. Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques. Expertise in Timing closure on high speed interfaces is a plus Excellent communication skills. Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure. Extensive experience and detailed knowledge in Cadence or Synopsys. Expertise in scripting languages such as PERL, TCL. Strong Physical Verification skill set. Static Timing Analysis in Primetime or Primetime-SI. Good written and oral communication skills. Ability to clearly document plans. Ability to interface with different teams and prioritize work based on project needs.

SI-PI Engineer : 5+ Years of experience with Strong knowledge in Signal Integrity and Power Integrity fundamental concepts . Strong experience in PCB modelling is required. Performs Transmission line & Via modelling and carry out experiments to validate modelling outcomes and methodologies. Deep Understanding of S-parameter & its modelling concepts for Single ended and differential interfaces. Experience in simulating (FD/TD) memory interfaces for Board and Package is required (DDR4/LPDDR4/DDR5/LPDDR5) Experience in simulating (FD/TD) High Speed Serial IO interfaces for Board and Package is required (PCIe Gen3/4, USB3/3.1 and MIPI CSI/DSI Interfaces etc.) System level simulation for Read & Write cases for eMMC/NAND Flash/SDIO System level simulation for HDMI signals with connectors & cable including CMC for all PVT corners Good knowledge of Power Delivery Network, impedance profile analysis, IR Drop Analysis, and time domain Analysis. Power Integrity Experience in extracting the PDN model of PCB power rails and perform decoupling capacitor optimization, Loop inductance analysis. Should be able to analyze and review the layout files related to Signal integrity and Power Integrity problems. Should be able to provide practical solutions to PCB/Package design team based on simulation results and analysis. Strong knowledge in simulation tools specifically Hspice, Power SI, Power DC , ADS and other tools like Ansys SIwave, HFSS 3D,

Experience into STA and timing closure/signoff experience with PD domain skill-set/knowledge. Candidate should be able to understand the timing constraints, analyze design details, analyze timing reports from prepcts to postcts stages, in-depth concepts of 14nm technode STA analysis, DCD knowledge. Candidate is preferably expert in PT and Tempus tools. Education Requirements B. Tech / M. Tech (ECE) Shift General Work Week Monday to Friday Joining time Immediate to 90 Days

He/She should be able to do block level / top-level floor planning, PG Planning, partitioning (for hierarchical designs) , placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks and be able to fix the violations . S hould have worked on 4 5nm , 28nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. Provide technical guidance, mentoring to physical design eng inee rs. Interface with front-end ASIC teams to resolve issues. Excellent communication skills. Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure. Extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools. Expertise in scripting languages such as PERL, TCL. Strong Physical Verification skill set. Static Timing Analysis in Primetime or Primetime-SI. Good written and oral communication skills. Ability to clearly document plans. Ability to interface with different teams and prioritize work based on project needs.

Must Have Skills Floor Planning/Innovus/Fusion Compiler Good to have Experience on programming in Tcl/Tk/Perl. Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. Mandatory Skills: VLSI Physical Place and Route.Location- Bangalore/ Pune/ Hyderabad/ Kochi

Understand and align the team's contributions with project goals, recognizing their impact within the project management framework Operate within financial and program constraints while considering budgetary implications in design options Develops construction cost estimates and estimates of technical efforts/ fee proposal for projects Work within the financial and programme constraints and consider financial implications in producing design options Performs quality control review of design documentation, calculations and drawing Lead EMI and E&B activities, offering guidance, support, and performance management Participates in development of technical proposals. Provides input to the development of engineering budget and schedule to meet requirements. Qualifications Master of Engineering degree (or equivalent education) in an appropriate engineering discipline from an accredited college or university. Chartered Engineer (CEng), or Professional Engineer (PE) license or equivalent in the relevant field from any global organization (e.g., Institution of Civil Engineers, UK) 12+ Years of experience Contribute to design development, design risk and mitigation, and value engineering with a focus on electromagnetic compatibility (EMC) and electromagnetic interference (EMI) Provide expert technical guidance and ensure adherence to earthing and bonding (E&B) standards throughout the design process Present EMC/EMI and E&B strategies effectively to stakeholders and non-technical leads Develop and deliver Earthing (Grounding) and Bonding Control Strategy reports Produce detailed design documentation, including calculations, design sketches, and technical specifications Participate in interdisciplinary design team meetings and coordinate with sub-consultants and equipment suppliers for accurate design information Review and verify design drawings and ensure they align with project requirements and standards Prepare technical reports and assess project specifications for construction compliance Provide input to E&B strategy and conduct power quality compatibility assessments Working with design engineers to advise on EMC test specifications and production of test procedures and reports as required Advise appropriate EMC solutions through design analysis to identify required control techniques and good design practice Earthing (Grounding) & Bonding Design: Produce comprehensive reports detailing solutions for each facility Produce calculation reports to justify results and ensure compliance with required values. Develop and mark up drawings, including grounding grid layouts, cross-sections, riser diagrams, and bonding drawings. Technical specifications of the elements Lightning Protection Design: Produce reports outlining solutions for each facility. Create calculation reports to validate results and meet compliance requirements Develop and Mark up drawings for lightning protection layouts and connections to main grounding grids. Define technical specifications for lightning protection elements. Ensure that technical and safety standards are maintained across all design activities tin order that successful project implementation and future reliability is achieved. Carry out risk assessments and provision of design information for Health and Safety file.

Expectations/ Requirements: l Key account Manager is principally responsible for Signing New Logos/ Merchants/Brands from Large Enterprise / Corporate Accounts. l The BDM achieves these goals by creating Funnel and Closure of accounts. Superpowers/ Skills that will help you succeed in this role: l Adaptability: Attitude of optimism and can-do orientation with ability to think creatively and navigate successfully past barriers and obstacles l Focus through the Noise: Ability to tune out distractions to focus work on priority goals and tasks l Persuasion: Ability to present concepts, ideas and proposals in a manner that is perceived positively by and clearly resonates with intended audiences and stakeholders, while encouraging action. l Professionalism: Ability to project a mature and professional attitude, demeanor and appearance as is appropriate to a given situation l Sense of Urgency: Ability to prioritize, plan and move decisively when necessary to meet timeframes to avoid timing crises.

The analyst will produce high-quality written content that communicates complex market dynamics clearly. Support insights with compelling visuals such as charts and graphs. The candidate will engage regularly with clients through calls, meetings, conferences, and events delivering tailored insights, explaining methodologies, and articulating value propositions. Responsibilities The analyst will conduct power modelling for power markets to deliver short-term market forecasts in client-facing reports. Key considerations in modelling may include, but are not limited to: Capacity build-up. Thermal fuel switching. Temperature-adjusted power demand. Power market mechanisms and price settlement methods. Carbon emission policy, cost, price and new technologies. Power and renewables policies, market trends and key players. Requirements A university degree in economics, business, public policy, or a related field. Familiarity with broader commodity markets, especially in the energy sector. Excellent English communication skills (reading/writing/speaking). Experience building forecasts or models. Knowledge of electricity markets in South and Southeast Asia. Experience with integrated cross-commodity analysis. Strong team players who can work across geographies and time zones. Proven ability to write clearly, visualize data effectively, and present complex analysis in high-level engagements and public forums. Having experience from a similar role is a plus.

Job Overview TE Connectivitys R&D/Product Development Engineering Teams conceive original ideas for new products, introduce them into practice. PCB engineer is scalable to contribute individually. He/she is responsible for delivering the project from schematic scratch till the board get fabricated. Stackup analysis, routing strategy, placement feasibility is more important. R&D engineer should familiarize in manufacturing process and the different soldering process, IPC standards for SMT & PTH library footprint creation. Responsible for all the documentation related to the board design and fabrication data. Typical fields of expertise include Analysing different dielectric materials, knowledge on high-speed design constraint, electrical, software, automation systems, data packaging, testing and measurement, and manufacturing of electrical, mechanical and electronic components, products, and their integration into systems. Responsibilities: TE Connectivity is seeking an experienced candidate for high speed printed circuit board design. The candidate is expected to interface with US and China based engineering teams for input and independently work on printed circuit board layout while also providing guidance and direction to local designers. The position requires that the candidate be able to utilize generalized engineering direction to create detailed custom designs. The candidate will be responsible for ensuring the accuracy and functionality of the end design and be able to take ownership of various aspects of the PCB design. Programs may additionally include pre-layout analysis and coordination of global vendors for prototype fabrication and assembly. Candidate Desired Profie Candidate should have excellent verbal communication skills, a high attention to detail, be highly motivated, a quick learner, and be able to work independently. Understanding of printed circuit board design, manufacturing, and assembly is required. Experience with printed circuit board design is required. Must be able to deliver the board design from scratch schematic to gerber release for manufacturing. Very good exposure in design software - Altium, Allegro, AutoCAD is must. Previous work experience in high-speed board designs will be highly preferred. Altium/Allegro tool scripting knowledge will be an added advantage for this role. Able to address supplier Engineering Queries. Familiarity with the following a plus: CAM350 High speed and/or RF circuits Signal integrity analysis Connectors and cable assemblies PCB manufacturing tolerances and cost drivers PDMLink process ECR/ECN release process Competencies

We are seeking a highly skilled and experienced Physical Design Engineer to join our team. The ideal candidate will have hands-on experience in chip-level and block-level physical design, timing closure, and signoff processes. This role requires proficiency in industry-standard tools and scripting, along with a strong understanding of design constraints and methodologies. Key Responsibilities: Perform chip-level floorplanning, partitioning, timing budget generation, and power planning.Execute top-level place and route (PnR), clock tree synthesis (CTS), block integration, and ECO generation.Handle block-level implementation from netlist to GDSII.Drive timing closure for high-frequency blocks and manage blocks with high instance counts (1M+).Ensure signoff closure for timing (including SI and OCV), power, IR drop, and physical verification.Apply signal integrity (SI) prevention and fixing methodologies.Conduct layout edits and physical design optimizations.Automate design tasks and manage UNIX-based environments. Primary Skills: Chip-level and block-level physical design expertise.Hands-on experience with Synopsys ICC and PrimeTime.Proficient in signoff closure for timing, power, IR, and physical verification.Strong understanding of SI and OCV impacts and mitigation strategies.Experience with high-frequency designs and large instance count blocks.Proficient in layout editing techniques. Secondary Skills: Familiarity with Mentor Olympus and Atoptech toolsets.Experience in design automation.Proficiency in UNIX systems.Scripting knowledge in Tcl and/or PERL. Educational Qualification: Bachelors or Masters degree in Electrical Engineering, Electronics, VLSI, or a related field.

We are seeking a highly skilled and experienced Physical Design Engineer to join our team. The ideal candidate will have hands-on experience in chip-level and block-level physical design, timing closure, and signoff processes. This role requires proficiency in industry-standard tools and scripting, along with a strong understanding of design constraints and methodologies. Key Responsibilities: Perform chip-level floorplanning, partitioning, timing budget generation, and power planning.Execute top-level place and route (PnR), clock tree synthesis (CTS), block integration, and ECO generation.Handle block-level implementation from netlist to GDSII.Drive timing closure for high-frequency blocks and manage blocks with high instance counts (1M+).Ensure signoff closure for timing (including SI and OCV), power, IR drop, and physical verification.Apply signal integrity (SI) prevention and fixing methodologies.Conduct layout edits and physical design optimizations.Automate design tasks and manage UNIX-based environments. Primary Skills: Chip-level and block-level physical design expertise.Hands-on experience with Synopsys ICC and PrimeTime.Proficient in signoff closure for timing, power, IR, and physical verification.Strong understanding of SI and OCV impacts and mitigation strategies.Experience with high-frequency designs and large instance count blocks.Proficient in layout editing techniques. Secondary Skills: Familiarity with Mentor Olympus and Atoptech toolsets.Experience in design automation.Proficiency in UNIX systems.Scripting knowledge in Tcl and/or PERL. Educational Qualification: Bachelors or Masters degree in Electrical Engineering, Electronics, VLSI, or a related field.

Will be technically driving team Custom Circuit IO and Datapath solutions for next generation Memory in advanced CMOS technology nodes. Will work on architecture of High speed IO and DataPath solutions to meet the specifications and product requirements Work closely with team and actively participate in technical discussions and reviews. Pro-actively get design issues/problems solved. Contribute to or propose innovative design solutions and design methodologies. Qualifications Bachelors/Masters degree in Electronics & Telecommunication/Electrical engineering Hand-on design knowledge on both analog & mixed signal design environment. 8+ years of Experienc

Will be technically driving team Custom Circuit IO and Datapath solutions for next generation Memory in advanced CMOS technology nodes. Will work on architecture of High speed IO and DataPath solutions to meet the specifications and product requirements Work closely with team and actively participate in technical discussions and reviews. Pro-actively get design issues/problems solved. Contribute to or propose innovative design solutions and design methodologies. Qualifications Bachelors/Masters degree in Electronics & Telecommunication/Electrical engineering Hand-on design knowledge on both analog & mixed signal design environment. 8+ years of Experienc

We are looking for technically sound and highly skilled High-speed SERDES IO PHY Layout designer with 12-15 years of experience. Apart from Serdes PHY Layout, the ideal candidate should have a strong background in analog/IO design principles, hands-on experience with layout tools, and a passion for solving challenging technical problems. Key Responsibilities: Develop and optimize Serdes PHY, analog and mixed-signal IC layouts, ensuring high performance and manufacturability. Collaborate with design engineers to understand design requirements and translate them into precise layouts. Strong experience in debugging DRC, ERC, LVS, EMIR and PERC issues independently. Work closely with the physical design team to integrate custom blocks into the overall chip design. Identify and resolve layout-related issues, providing creative solutions to meet design specifications. Conduct design reviews and provide technical feedback to improve layout practices and methodologies. Stay up-to-date with industry trends, tools, and technologies to continuously enhance layout processes. Qualifications 12-15 years of experience in Serdes Phy, Analog and Mixed-signal IC layout design. Proficiency in layout tools such as Cadence, Synopsys, or Mentor Graphics. Hands-on experience with custom layout design for various Serdes Phy, Analog and IO circuits is required, including expertise in Bandgap references, LDOs, Clocking circuits, GPIOs, DDR IOs. Familiarity with custom digital layout (i.e. high speed logic paths). Knowledge of signal integrity issues (i.e. clock/data routes, differential routing, shielding). Strong understanding of analog/IO design principles, including circuit performance and parasitic effects. Aware of layout techniques to mitigate ESD, latch-up issues. Holds advanced knowledge of CMOS and FinFET technologies and their impact on design and performance issues in deep sub-micron process nodes, specifically 5nm and below. Experience with layout concepts that incorporate reliability considerations, including techniques for managing electromigration (EM), IR drop, and self-heating. Experience with layout optimization for power, performance, and area (PPA) metrics. Excellent problem-solving skills and attention to detail. Effective communication and teamwork abilities. Preferred Skills: Knowledge of scripting languages (e.g., Skill,TCL and SVRF) for automation tasks. Qualifications Bachelor s or Master s degree in Electronics or Electrical Engineering

Design and develop complex multilayer PCB HDI layouts (analog, digital, RF, power electronics) as per layout guidelines. Creating ECU layouts for automotive applications Collaborate with hardware engineers, signal integrity experts, and manufacturing teams to ensure designs meet performance, manufacturability (DFM), and testability (DFT) requirements. Worked on high-speed PCB design, impedance control, power planes, and signal integrity. Participate in design reviews, continuous improvement initiatives. Interface with PCB manufacturers and vendors for prototype procurement and cost optimization.

Actively contribute to provide Custom Datapath solutions for next generation Memory in advanced CMOS technology nodes. Designing Datapath (custom and/or RTL) Blocks, Full chip Timing Finesim Design closure to meet the specifications and product requirements Work closely with team and actively participate in technical discussions and reviews. Pro-actively get design issues/problems solved. Contribute to or propose innovative design solutions and design methodologies. Qualifications Bachelors/Masters degree in Electronics & Telecommunication/Electrical engineering (VLSI Design) Hands-on design knowledge on both Digital custom, Analog & mixed signal design environment. 4+ years of Experience on IO circuit blocks used in memory products like DDR4, DDR5, LPDDR4, LPDDR5, GDDR5, GDDR6 is desirable. NAND Flash Design knowledge is plus Familiar with custom design methodology & flow, Calibration, JTAG design requirements, understanding of High-speed IO circuit and Datapath design including DLL, Rx, Tx and clocking circuits Knowledge of High Speed layout guidelines, analog layout techniques, including floor-planning, matching, shielding and parasitic optimization Understanding Datapath circuits like pipelining, digital design, STA, fan-out and load estimation, FIFO design etc.. Familiarity with package/board/Power integrity /signal integrity constraints is a plus. Strong communication skills & circuit design knowledge is preferred. Tool knowledge: spice tools: finesim, hspice & other flows Good automation & scripting knowledge is plus.

We are seeking a Senior Manager, Hardware Development Engineering to join our innovative team in Bengaluru, India. In this role, you will lead and oversee the Signal Integrity, Power Integrity, electrical validation, driving technological advancements and ensuring the delivery of high-quality products. Lead and manage a team of SI/PI, Validation engineers, providing technical guidance and mentorship for Sandisk's retail product group that covers products like USB, portable SSD, SD/uSD/Express cards etc Develop and implement SI/PI strategies aligned with organizational goals Collaborate with cross-functional teams to define product requirements and specifications Analyze and resolve complex technical issues in hardware design and development Manage project timelines, budgets, and resources effectively Stay up-to-date with emerging technologies and industry trends Present technical proposals and progress reports to senior management Foster a culture of innovation and continuous improvement within the team Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, or related field; Master's degree preferred 15+ years of experience in hardware development engineering, with 3+ years in a managerial role Proven track record in leading successful hardware development projects Strong expertise in extraction tools like HFSS, Hyperlynx etc and hands on experience with simulation tools like HSPICE, ADS etc Sound knowledge of SERDES interfaces, NAND/DRAM, optimizing power integrity etc. In-depth knowledge of hardware design principles and manufacturing processes Excellent project management skills; PMP certification is a plus Experience with product lifecycle management Strong analytical and problem-solving abilities Exceptional leadership and team management skills Excellent communication and interpersonal skills Domain expertise in consumer electronics, telecommunications, or industrial automation Ability to work effectively in a fast-paced, dynamic environment