Principal Physical Design Engineer

About the role:

• Interconnect floor planning iterations, partitioning, pin-placement, wire planning, clock distribution network.
• Working with Architecture, RTL and timing teams for optimal floorplan from system performance point of view.
• Implement power and clock domain crossing with UPF and timing methodologies.
• Converge timing on high speed interface with appropriate methods of clock balancing and skewing.
• Lead and execute physical design tasks for CPU/GPU blocks including floor planning, placement, clock tree synthesis, routing, and optimization.
• Collaborate with RTL designers and timing engineers to achieve timing closure, power targets, and area goals.
• Perform physical verification and signoff checks ensuring design compliance with foundry rules and design specifications.
• Analyze and resolve physical design issues such as congestion, timing violations, and signal integrity challenges.
• Develop scripts and automation flows to improve design efficiency and quality.
• Address interconnect-related challenges such as crosstalk, IR drop, electromigration, and noise.
• Document design methodologies, best practices, and integration guidelines specific to Ampere s CPU/GPU physical design flows.
• Collaborate and work with cross geo teams in India & Vietnam

About you:

• Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work.
• Generous paid time off policy so that you can embrace a healthy work-life balance
• Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day.