Senior Edge AI Engineer

About the role:

Experienced Edge AI Engineer to design, optimize and deploy computer-vision and real-time ML applications on resource-constrained embedded hardware (Renesas RZ/V series, RA/RA8P1, Jetson, STM32, NXP/Infineon MCUs, etc). The role owns the end-to-end AI lifecycle on board (model -> optimization -> deployment -> embedded pipeline) and is responsible for production-grade integration, profiling and delivery of model artifacts and embedded software for field devices.

Primary responsibilities:

• Design and develop AI/ML applications for edge devices with a strong focus on embedded deployment (RZ/V2H, RA8P1, RA6, STM32, Jetson, etc.).
• Port and optimize neural networks for real-time inference on constrained MCUs/MPUs and NPUs: conversion, quantization (PTQ/QAT), pruning, layer fusion and operator mapping.
• Convert and prepare models for embedded runtimes (ONNX, TFLite, TorchScript, TVM/DRP-AI, TensorRT) and integrate with runtime stacks (ONNX Runtime, TFLite-Micro, custom inference engines).
• Develop and maintain C/C++ embedded application layers that host the inference engine and handle sensor I/O, DMA, framebuffers, and real-time buffering.
• Implement and run benchmarking, profiling, and verification tests (latency, throughput, memory footprint, power) across multiple platforms and configurations.
• Design pre & post-processing logic for vision outputs and integrate into application stack.
• Produce reproducible artifacts: e2s / map files, model cards, benchmark reports, code stubs and deployment guides.

Required skills & experience:

• 5+ years professional experience building and deploying deep learning solutions; significant hands-on experience on edge/embedded platforms.
• Proficiency in C and C++ for embedded application development and performance critical components.
• Basic Python skills for ML work (PyTorch, TensorFlow/Keras) - model conversion and optimization.
• Experience integrating Edge AI models into constrained MCU environments.
• Hands-on with ONNX, TVM, TFLite/TFLite-Micro, TensorRT or similar conversion & inference toolchains; experience with DRP-AI / RUHMI / MERA or equivalent is a strong plus.
• Deep practical knowledge of model optimization techniques: PTQ & QAT, weight pruning, distillation, operator fusion, INT8 calibration, mixed precision.
• Experience with ARM-based MCUs/MPUs (Renesas, STMicro, NXP) and embedded Linux / Yocto / buildroot environments.
• Strong Computer Vision expertise (object detection, classification, segmentation) and use of OpenCV / image pipelines.
• Strong debugging skills, especially with imperfect libraries, and ability to identify and report issues effectively.
• Knowledge of low-level optimization and hardware/software co-design is a plus.