Job
Description
Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high-quality integration and verification of the IP block. Drives quality assurance compliance for smooth IP SoC handoff. Key Responsibilities: Design and develop cache architectures, including L1, L2, and L3 caches. Optimize cache performance, power, and area through innovative design techniques. Work closely with backend (BE) engineers to achieve timing closure and resolve any issues. Conduct static timing analysis (STA) and optimize the design for timing. Utilize lint, CDC (Clock Domain Crossing), and other design tools to ensure design quality and robustness. Implement and adhere to best practices in RTL design Collaborate with microarchitecture, RTL, verification, and physical design teams to ensure seamless integration of cache subsystems. Document design specifications, implementation details, and verification results. Participate in design reviews and provide feedback on other team members' designs. Qualifications Bachelor's or master's degree in electrical engineering, Computer Engineering, or a related field. 5-15 years of proven experience in design and micro-architecture. Strong understanding of memory hierarchy, cache coherence, and performance optimization techniques. Proficiency in hardware description languages (HDL) such as Verilog or VHDL. Experience integrating BIST and DFT features into RTL designs. Experience implementing Error Correction Code (ECC) mechanisms in cache designs. Knowledge of error detection, correction, and recovery techniques. Experience with simulation and verification tools (e.g., ModelSim, VCS). Experience using lint, CDC, and other design tools to ensure design quality. Proficiency in static timing analysis (STA) and timing closure techniques. Familiarity with physical design constraints and considerations. Excellent problem-solving skills and attention to detail. Strong communication and teamwork abilities.
