571 Rtl Design Jobs - Page 19

Emulation Engineer Experience3 to 5 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: should have emulation experience working on available platforms such as; Palladium, Veloce, or Zebu, as well as experience with compilation, debug, performance, and throughput tuning Experience using Verilog, VHDL design Experience with C/C++ and System Verilog, UVM verification environments Experience writing scripts using Perl, Python, Makefile Debugging experience using tools like waveform, Verdi, Simvision Strong communication skills and ability to work as a team Description You’ll support multiple emulation environments using the latest emulation techniques (C/C++ DPI Transactors, SV assertions, Coverage, Power Estimation, SpeedBridges, Accelerated UVM Testbenches). You’ll be bringing up SOCs on emulation, root causing SoC/Processor test fails and emulator environment issues. – We are in constant collaboration with Design, DV, Power, Silicon Validation, Performance, and Software teams. – Your strong design, debug, communication, and teamwork skills will be essential. – You will also work with leading emulation vendors to debug issues. Skills Experience Zebu Verilog, Python Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore USADelaware USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

Pre-Silicon Validation Engineer Experience4 to 10 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: Creating test environments, checker strategies, and test generators for validating embedded power management firmware in the SOC Communicating effectively, coordinating and working with firmware developers and SOC integration teams Potentially participating in the debug of failures in silicon and developing new testing strategies to detect these failures on pre-silicon models Mentoring junior members of the team in their development You should have 3-5 years of experience in the following areas: SoC development, verification, or integration using Verilog/SystemVerilog/OVM/UVM Reading and interpreting technical specs and Register Transfer Level (RTL) code SW development skills (Unit Testing, Test Driven Development) Hands-on Debug Preferred Skills and Experience: Expertise in any of one domain like Audio, Performance, power management will be a huge plus 4+ years’ experience with writing validation plans and implement those validation plans Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

SR. DFT ENGINEER SmartSoC is looking for expert DFT engineers for the development, support, maintenance, Implementation, and Testing of complex components of an ASIC/SOC/FPGA/Board. Desired Skills and Experience- 3 – 10year’s experience in DFT Good experience/concept on all aspects of DFT i.e. SCAN/ATPG, MBIST, Boundary Scan. DFT logic integration and verification. Experience in debugging low coverage and DRC fixes Gate Level ATPG simulation with and without timing. Pattern generation, verification, and delivery to ATE team. Post silicon debug and support on failing patterns. Good experience with tools from Mentor/Synopsis/Cadence. LBIST experience is plus. DFT mode STA and timing closure support. Familiarity with Verilog and RTL simulation Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

About Applied Applied Materials is the leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. Our expertise in modifying materials at atomic levels and on an industrial scale enables customers to transform possibilities into reality. At Applied Materials, our innovations make possible the technology shaping the future. Your Opportunity As an EE you will be working in highly technical, flexible environment with top level exposure to all cutting-edge technologies and legacy system. You will have the opportunity to engage in the Product Life Cycle from concept designs to volume manufacturing for the modules/systems enabling to solve the High value problems of our customers. You will be offered unique opportunities and challenges to get interfaced with our customers and suppliers. Applied continues to grow and is the #1 Semiconductor Manufacturing Company in the industry. Key Responsibilities Expert level technical support in the resolution of FPGA design and application issues Design or modify electrical/electronic engineering assemblies, layouts/schematics and/or detailed drawings/specifications of moderate scope under general supervision. Create design and specification documents, test plans and progress reports. Conduct obsolescence risk assessment for prompt risk mitigation strategy and implementation to ensure product manufacturability and sustenance. Coordinate the procurement and assembly of electrical/electronic components/equipment and identify sources of critical parts and subsystems to resolve technical issues. Participate in resolving customer complaints & escalations through root-cause analysis and corrective-preventive actions. Functional Knowledge (Required Skills/Experience): Extensive knowledge of RTL design language. Hands on experience on design, simulation and testing of FPGA application. Good knowledge of electrical design engineering, Digital/Analog/Mixed signals, Power electronics, Controls and Instrumentation. Good knowledge of electrical engineering design concepts and applications - components, schematics, electrical system. Good understanding on communication interface such as I2C, SPI, USB, Wi-Fi, IoT and Bluetooth, memory device such as SRAM, DDR3+, and high speed communication protocols such as ETHERCAT, ETHERNET, PCIe Experience on microcontrollers and microprocessor design. Interpersonal Skills Demonstrate strong written, oral, and interpersonal communication skills. Excellent aptitude for multi-tasking and willing to learn. Qualifications Bachelors Degree in Electrical Engineering / Electronics & Communication Qualifications Education: Bachelor's Degree Skills: Certifications: Languages: Years of Experience: 4 - 7 Years Work Experience: Additional Information Time Type: Full time Employee Type: Assignee / Regular Travel: Yes, 10% of the Time Relocation Eligible: Yes Applied Materials is an Equal Opportunity Employer committed to diversity in the workplace. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.

- Lead the architecture, design and development of Power Management for a highly virtualized, multi-threaded, many-core and multi-socket SMP (symmetric multi-processor) . - Develop the features, present the proposed architecture in the High level design discussions to hardware and software teams - Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, firmware, software teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Estimate the overall effort to develop the feature - Estimate the silicon area required for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8 or more years of demonstrated experience in architecting and designing Server SoC power management features. * Experience with hardware to model correlation * At least 1 generation of silicon bring up experience * In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) * Proficiency of RTL design with Verilog or VHDL * Knowledge of at least one object oriented or functional programming language and scripting language. Preferred technical and professional experience Hiring manager and Recruiter should collaborate to create the relevant verbiage.

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-8 years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique One Cadence - One Team culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other every day. Job responsibilities: BE/BTECH/ME/MTECH Or Equivalent Degree EXP:10-18yrs Primarily working for Roadmap project MRDIMM Controller for CHI Address channel Multiplexing RTL Design, Verification and Synthesis Support. Work to achieve MRDIMM Controller for CHI Address channel Multiplexing Feature s Optimal PPA (Performance, Timing and Area) We re doing work that matters. Help us solve what others can t.

Full time with century old top Japanese MNC JOB SUMMARY ( Full time with Super Top Japanese MNC) JDs follow for following roles, Principal Engineer VLSI Semiconductor Chip Design Analog Principal Engineer VLSI Semiconductor Chip Design Backend Principal Engineer VLSI Semiconductor Chip Design Frontend ------------------------------------------------------------------------------------------------------------------------------------------ Job Title : Principal Engineer Chip Design Analog Job Title: Principal Engineer - Analog IP/IC Job Overview: As an Principal Engineer - Analog IP/IC specializing in Semiconductor Chip Design, you will lead and coordinate the execution of analog and mixed-signal integrated circuit development projects. This role requires a strong technical background in analog design, verification, and physical implementation, coupled with exceptional project management skills. You will oversee teams engaged in designing high- performance analog circuits, ensuring precision and reliability in semiconductor designs. Key Responsibilities: Design analog/mixed-signal blocks: ADC/DAC, PLL, LDO/DCDC, IO, Motor & Gate Drivers . Run MATLAB modeling , circuit simulations , and post-layout analysis (LPE, Monte Carlo). Develop and manage verification plans , mixed-signal simulation , and behavioral models . Guide custom layout and ensure DRC/LVS/ESD/DFM compliance. Collaborate with digital, verification, layout, and test teams. Use industry-standard EDA tools (e.g., Custom Compiler). Product Support Required Skills & Experience Required Skills & Experience Min 8+ years of experience in custom analog/mixed signal design Strong in variation-aware design, verification planning, and cross-functional teamwork. Layout Parasitic Extraction (LPE), Custom IC Design, EDA Tools for Analog Design Strong design and debugging skills. Experience in Product Support for both Pre and Post Production Stages, Support for RMA teams. Preferred Skills and Experience Min 1+ years of Project Management (Waterfall and Agile Hybrid Methodology). Continuous Improvement. Qualifications: Masters in VLSI design from reputed universities like IIT/NIT with a background in Bachelors in Electronics and Communication, or a related field ------------------------------------------------------------------------------------------------------------------------------------------------------ Job Title : Principal Engineer Chip Design Back End Job Overview: : As a Backend (Physical Design) Principal Engineer specializing in Semiconductor Chip Design, you will lead and coordinate the execution of the back-end stages of integrated circuit development. This role requires a strong technical background in physical design, a deep understanding of semiconductor processes, and exceptional project management skills. You will oversee teams engaged in physical design, synthesis, DFT, place and route, power integrity, and other back-end aspects to ensure the successful realization of semiconductor designs. Additionally, you will oversee product support activities for both Pre-production and Post-production stages, ensuring the successful initiation, development, and sustainment of semiconductor designs. Key Responsibilities: Technical Leadership - Own synthesis, SDC constraint development, and formal verification. - Drive place & route (P&R) including floorplanning, CTS, and timing closure. - Optimize for power, performance, and area (PPA); manage power distribution and multi-voltage design. - Lead STA across corners/modes and support technology node migration. - Integrate and verify SCAN/MBIST, define test specifications, and debug test coverage issues. - Perform DFM, DRC, and ESD checks to ensure manufacturability. - Collaborate with cross-functional teams (Frontend, Analog. - Document design flow, participate in design reviews, and mentor junior team members. - Product Support and RMA support Required Skills & Experience - Min 8+ years of strong experience in backend flows for MCU or low-power SoC designs . - Ability to lead the DFT teams, Physical and formal Verification Teams. - Exposure to frontend and Analog processes. - Ability to collaborate effectively with frontend and analog teams - Experience in Product Support for both Pre and Post Production Stages, Support for RMA teams. Preferred Skills and Experience - Min 1+ years of Project Management (Waterfall and Agile Hybrid Methodology). - Continuous Improvement. - Knowledge of industry standards and best practices in semiconductor front-end design. Qualifications: Masters in VLSI design from reputed universities like IIT/NIT with a background in Bachelors in Electronics and Communication, or a related field. ---------------------------------------------------------------------------------------------------------------------------------------------- Job Title : Principal Engineer – Chip Design Front End Job Overview: As a Frontend Principal Engineer specializing in Semiconductor Chip Design, you will lead and coordinate the execution of the front-end stages of integrated circuit development. This role requires a strong technical background in digital design, verification, and project management skills. Additionally, you will oversee product support activities for both the Pre-production and Post-production stages, ensuring the successful initiation, development, and sustainment of semiconductor designs. Key Responsibilities: Technical Leadership and Architecture Design Architecture from scratch for new products and understand the specifications of the derivative products. RTL Design and Coding, Code Quality Management : Creating RTL Design and Coding.. Ensure highest quality by applying suitable coding standards and other techniques. Design Verification : Ensuring the correctness and functionality of the design through rigorous verification processes. This includes creating test benches, running simulations, and debugging the design. Collaboration : Working closely with other teams, such as physical design, analog IP/IC, software, and system engineering teams, to ensure seamless integration and functionality of the final product. Mentorship and Leadership : Leading and mentoring junior engineers, providing guidance on best practices, and ensuring the team adheres to project timelines and quality standards. EDA Tools Proficiency : Utilizing EDA tools for design, simulation, and verification tasks. Documentation : Maintaining detailed documentation of the design process, including specifications, design decisions, and verification results Product Support : Pre and Post Production Stages, Support for RMA Required Skills & Experience - Min 8+ years of experience in System Architecture for ARM based MCU product development - Min 8+ years of experience in RTL Design, Coding and RTL Integration, - Strong design and debugging skills. - Experience in handling Verification Teams. Verification environment Development , Static and Dynamic Verification, Test Management. (UPF, GLN, Test Mode) - Experience with industry-standard EDA tools for LINT, CDC, SDC validation, and power analysis preferably Synopsis EDA. - Exposure to Backend and Analog processes. - Ability to collaborate effectively with backend teams (PD, DFT, and STA) to achieve timing and power closure. - Experience in Product Support for both Pre and Post Production Stages, Support for RMA teams. Preferred Skills and Experience - Min 1+ years of Project Management (Waterfall and Agile – Hybrid Methodology). - Continuous Improvement. - Knowledge of industry standards and best practices in semiconductor front-end design. Qualifications: Masters in VLSI design from reputed universities like IIT/NIT with a background in Bachelors in Electronics and Communication, or a related field

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique One Cadence - One Team culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other every day. Job Summary: We are looking for 14+ years of experience having the following skillset: Strong RTL design fundamentals using HDLs like VHDL/Verilog/System verilog Strong understanding of AMD (Xilinx) ultrascale, versal FPGAs architecture and use of vivado for FPGA place and route. Constraints definitions for FPGAs. Doing Static Timing Analysis. Familiarity with FPGA prototyping or emulation is a plus. Passionate to learn and explore new technologies and demonstrates good analysis and problem-solving skills. Good written and verbal communication skills, should be a quick learner and a team player. We re doing work that matters. Help us solve what others can t.

Greetings from Wafer Space! Exciting Opportunity for Senior RTL Design Lead Engineers Automotive SoC Domain Job Title: Senior RTL Design Engineer No. of Positions: 4 Notice Period: Immediate to 30 Days Only Referrals: Please refer only suitable and relevant profiles About the Role: We are looking for experienced RTL Design Engineers to join our team developing next-generation solutions for automotive camera and display systems. This is a key position requiring strong technical expertise in microarchitecture and RTL coding, with an emphasis on high-performance, low-power ASIC designs. Key Responsibilities: Define microarchitecture and implement RTL to meet performance, power, and area (PPA) goals. Collaborate with software teams to define hardware/software interfaces, configuration requirements, and verification collaterals. Partner with verification teams on assertion development, test plans, debugging, and coverage closure. Ensure adherence to industry-standard ASIC design methodologies. Drive design quality and functional safety for automotive-grade solutions. Required Skills & Qualifications: Bachelors/Masters/Ph.D. in Electrical/Electronics Engineering. 5–10 years of hands-on experience in RTL design and microarchitecture development. Strong proficiency in Verilog and SystemVerilog. Proven experience in designing IP blocks for video/audio pipelines. Sound understanding of MIPI CSI and DSI protocols. Experience with high-speed, pipelined, and low-power designs. Familiarity with EDA tools and design methodologies (e.g., Synopsys, Cadence). Experience working on designs complying with automotive functional safety (ISO 26262) is a plus. Excellent problem-solving, communication, and team collaboration skills. Note: Only candidates with a notice period of 30 days or less will be considered. Please share or refer profiles that are strictly relevant to the requirements.

Develop verification environments for our ICs using Universal Verification Methodology (UVM); Job Description In your new role you will: create and define verification plans; develop verification environments for our ICs using Universal Verification Methodology (UVM); draw on test scenarios using SystemVerilog; verify functionality using the Constrained Random approach; develop assertions in SystemVerilog for formal verification; Interact with other disciplines, such as Concept and ApplicationEngineering, to define verification plans and strategies; provide proactive support to users of our verification flowenvironment; be responsible for our verification methods; Your Profile You are best equipped for this task if you have: You have successfully completed a university degree in Electrical Engineering, Computer Science or a similar academic discipline; You have at least 3 years of experience in Constrained-Random Metric-Driven Verification You have capabilities and experience in working withmicrocontroller-based ICs, as well as security and safety requirements; You have good know-how with UVM especially using SystemVerilog; Have knowledge of firmware and RTL design (VHDL); Ideally have knowledge of working with Verification IPs (VIPs) Contact: swati.gupta@infineon.com We are on a journey to create the best Infineon for everyone.

. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. . 3-10 years of experience in RTL design and Design Verification implementation for VLSI systems.

Defining and developing ASIC RTL verification at both chip and block levels. Creating and executing verification plans for complex digital designs, particularly focusing on PCIe/CXL protocols. Collaborating with cross-functional teams to ensure seamless integration and functionality of designs. Utilizing advanced verification methodologies and tools to achieve high-quality results. Mentoring and guiding junior engineers, promoting best practices, and fostering a culture of continuous improvement. Communicating with internal and external stakeholders to align on project goals and deliverables. The Impact You Will Have: Enhancing the reliability and performance of Synopsys digital verification processes. Improving time-to-market for robust Synopsys Interface IP controller through efficient verification methodologies. Mentoring and nurturing a highly skilled verification team, elevating overall project quality. Influencing strategic decisions that shape the future of Synopsys capabilities. Ensuring that Synopsys remains a leader in the semiconductor industry through continuous technological advancements. What You'll Need: Extensive experience in ASIC RTL verification. In-depth knowledge of PCIe, CXL , UCIe and similar IO protocols. Proficiency in advanced digital design verification tools and methodologies. Strong problem-solving skills and the ability to work independently. Excellent communication skills for effective collaboration with diverse teams. Experience of 18+ years in relevant domain.

You have a keen eye for detail and can identify design/architecture pitfalls across clock/reset domain crossings . Your ability to synthesize designs and ensure RTL and gate equivalence through formality checks is unmatched. You are a collaborative team player, ready to integrate IPs in SoCs/Subsystems and create RTL designs that meet customer needs. If you are ready to leverage your expertise in a role that shapes the future of semiconductor design, Synopsys is the place for you. What You'll Be Doing: Perform RTL Quality Signoff Checks such as LINT, CDC, and RDC. Understand design/architecture and develop timing constraints for synthesis and timing . Run preliminary synthesis to ensure design can be synthesized as intended. Run formality to ensure equivalence of RTL and gates . Integrate IPs in SoCs/Subsystems and create RTL design as per customer needs. Collaborate with cross-functional teams to deliver high-quality RTL designs. The Impact You Will Have: Ensure high-quality RTL Signoff for semiconductor designs. Contribute to the development of cutting-edge semiconductor technologies. Improve design efficiency and performance through effective timing constraints. Enhance the reliability and functionality of SoCs and subsystems. Support customer success by delivering tailored RTL designs. Drive innovation in RTL Design and Verification methodologies.

You are a seasoned professional in RTL Design and Signoff , bringing a wealth of experience and expertise to the table. You have a keen understanding of the complexities of RTL Quality Signoff and are adept at proposing resource requirements to meet project goals. Your leadership skills are top-notch, allowing you to guide a team of engineers through various pre-silicon static verification activities on IPs/Subsystems . You have a strong grasp of design and architecture , enabling you to develop precise timing constraints for synthesis and timing . Your ability to ramp up on new RTL Design and Static Verification tools and methodologies using Synopsys Products ensures that you stay ahead of the curve. You collaborate effectively with peers to enhance methodology and execution efficiency. Your excellent communication skills facilitate smooth interactions with Synopsys customers, BU AEs, Sales teams, and other stakeholders. With a minimum of 8+ years of experience , you are well-versed in debugging, diagnosing violations, and setting up flows and methodologies for quick RTL Signoff tool deployment . Your technical expertise in LINT, CDC, RDC, and timing constraints development is unparalleled. You are a strategic thinker with a strong understanding of design concepts, ASIC flows, and stakeholder management . What You'll Be Doing: Work with Synopsys customers to understand their needs and define RTL Signoff and design scope and activities. Understand the complexity and requirements of RTL Quality Signoff and propose resource requirements to complete the activities. Lead a team of engineers to perform various pre-silicon static verification activities on IPs/Subsystems. Develop timing constraints for synthesis and timing while understanding the design/architecture. Collaborate with peers to improve methodology and enhance execution efficiency. Ramp up on new RTL Design and Static Verification tools and methodologies using Synopsys Products to enable customers. Work with other Synopsys teams, including BU AEs and Sales, to develop, broaden, and deploy Tool and IP solutions. Set up flows and methodologies to enable quick setup for RTL Quality checks, Synthesis, and Formality. Train the team in design concepts and root-cause analysis. The Impact You Will Have: Ensure high-quality RTL Signoff and design, contributing to the success of Synopsys projects. Lead the team in delivering precise and efficient pre-silicon static verification activities. Enhance the overall execution efficiency of RTL Design and Signoff processes. Enable customers to achieve their goals through the deployment of Synopsys Products and methodologies. Develop and implement innovative solutions for RTL Quality Signoff in the semiconductor industry. Strengthen Synopsys reputation as a leader in chip design, verification, and IP integration. What You'll Need: B.E/B.Tech/M.E/M.Tech in electronics with a minimum of 8+ years experience in RTL Design and Verification. Technical expertise in various aspects of RTL Design and Signoff: LINT, CDC, RDC. Technical expertise in setting up flows and methodologies for quick deployment of RTL Signoff tools. Technical expertise in debugging and diagnosing violations and errors. Technical expertise in developing timing constraints and running preliminary synthesis for timing constraints check and area estimation. Ability to lead a team to perform RTL Signoff on complex SoC/IP/Subsystem. Experience with planning and managing various activities related to RTL Signoff and Design. Strong understanding of design concepts, ASIC flows, and stakeholders. Good communication skills.

You are a highly experienced and motivated professional with a solid background in SoC RTL Design . With over 12 years of experience , you have honed your skills in RTL Design, Lint, CDC, RDC, Synthesis, and Constraints Development . You possess a deep understanding of design concepts, ASIC flows, and stakeholder management . Your technical expertise allows you to debug and diagnose violations and errors, set up flows and methodologies for RTL Signoff tools, and develop timing constraints . You are an effective leader, capable of managing and growing a team, providing continuous feedback, and improving the quality of deliverables . Your excellent communication skills help you interact with customers, peers, and management to understand needs, report status, and resolve issues efficiently. What You'll Be Doing: Manage and lead a team of 7-8 SoC/Subsystem RTL Design Engineers for various customer engagements. Work with Synopsys customers to understand their needs and define RTL Signoff and design scope and activities . Lead the team to perform various RTL Design and Signoff activities for SoC Subsystems such as SoC u-Architecture and Integration, RTL Design (Verilog/SystemVerilog), Lint, CDC, RDC, Synthesis, Constraints Development. Assist and mentor the team in day-to-day activities and grow the capabilities of the RTL Design team for future assignments. Review various results and reports to provide continuous feedback to the team and improve the quality of deliverables. Report status to management and provide suggestions to resolve any issues that may impact execution. Understand the complexity and requirements of RTL Quality Signoff and propose resource requirements to complete the activities. Work with peers to improve methodology and improve execution efficiency. Collaborate with other Synopsys teams including BU AEs and Sales to develop, broaden, and deploy Tools. Train the team in design concepts and root-cause analysis. The Impact You Will Have: Drive the successful delivery of SoC Subsystems by leading a skilled team of RTL Design Engineers. Enhance the quality and efficiency of RTL Design and Signoff processes through continuous feedback and methodology improvements. Ensure customer satisfaction by understanding their needs and delivering high-quality solutions. Contribute to the growth and development of the RTL Design team, expanding their capabilities for future projects. Support Synopsys reputation as a leader in chip design and verification through successful project execution. Foster collaboration and innovation within the team and across different Synopsys departments. What You'll Need: B.E/B.Tech/M.E/M.Tech in electronics with a minimum of 12+ years of experience in SoC RTL Design . Technical expertise in various aspects of RTL Design and Signoff: LINT, CDC, RDC. Technical expertise on setting up flows and methodologies for quick deployment of RTL Signoff tools. Technical expertise in debugging and diagnosing violations and errors. Technical expertise in developing timing constraints and running preliminary synthesis for timing constraints check and area estimation. Ability to lead and manage a team to perform RTL Signoff on complex SoC/Subsystem. Experience with planning and managing various activities related to RTL Signoff and Design. Strong understanding of design concepts, ASIC flows, and stakeholders. Good communication skills.

You are a highly motivated and experienced ASIC Digital Design Engineer with a strong background in digital design for high-speed serial interfaces . You have a deep understanding of USB, PCIe, Ethernet, Display, and HDMI protocol standards , and you thrive in a collaborative environment. Your expertise in Verilog RTL design, microarchitecture, and timing constraints development makes you a valuable asset to any team. You are adept at using tools like Spyglass for CDC/RDC/Lint and have excellent debugging skills. Your ability to propose and implement design updates based on various requirements, coupled with your experience in test coverage and physical design timing closure , sets you apart as a leader in your field. With a passion for innovation and a keen eye for detail, you are ready to take on new challenges and contribute to the success of Synopsys. What You'll Be Doing: Driving and working on digital design for high-speed serial interface PHY IPs for USBx, PCIex, Ethernet, Display, and HDMI protocol standards. Proposing micro-architecture of design/design updates based on customer requirements, analog requirements, system performance improvements, Link layer interface changes, or overall robustness of design. Implementing RTL in Verilog and running Spyglass CDC/RDC/Lint. Collaborating with verification teams to test desired functionality and corner cases. Developing timing constraints, DFT insertion, and test coverage , and closing timing with physical design teams. Well versed in Micro-Architecture and Block Ownership, Design from scratch. The Impact You Will Have: Enhancing the performance and reliability of high-speed serial interface PHY IPs. Contributing to the development of cutting-edge technologies that power modern electronics. Driving innovation in digital design and influencing the future of semiconductor technology. Collaborating with cross-functional teams to deliver robust and high-quality designs. Ensuring that Synopsys remains a leader in the semiconductor industry through continuous improvement and excellence. Supporting customers by providing high-performance and reliable IP solutions that meet their needs. What You'll Need: 5-8 years of relevant experience in digital design for ASICs. Strong knowledge of Verilog RTL design and microarchitecture. Experience with timing constraints development and synthesis flow. Proficiency in using Spyglass or similar tools for Lint/CDC/RDC. Proficiency in scripting and automation using TCL, PERL, or Python. Excellent debugging skills and attention to detail. Who You Are: A collaborative team player with strong communication skills. A problem solver with a proactive approach to challenges. A detail-oriented professional with a passion for innovation. A self-motivated individual who thrives in a fast-paced environment. An adaptable engineer who can handle multiple tasks and priorities.

What You ll Need: EE graduate from a reputed school, with post-graduate qualifications preferred. 15+ years of industry experience in RTL design or verification using simulation-based technologies. 5+ years of experience managing medium to large-sized teams. In-depth understanding of Assertion-based verification using formal and simulation methods. Strong knowledge of hardware design (Verilog/VHDL) and micro-architecture. Expertise in Unix/Linux automation shell (bash, csh) and scripting (Tcl, Perl, Python). Excellent oral and written communication skills. Expertise in one or more areas such as Formal Property Verification testbench development, floating point arithmetic operations, C/C++, IEEE math libraries, Security architecture, Automotive Safety (FuSa) verification, and Verification signoff with formal.

Description We are seeking a highly skilled ASIC Physical Design, Sr Staff Engineer to join our team in India. In this role, you will be responsible for the physical design and implementation of high-performance ASICs, collaborating closely with cross-functional teams to ensure successful project delivery. Responsibilities Design and implement physical layouts for ASIC designs. Conduct place and route activities to meet timing and area requirements. Perform timing analysis and optimization to ensure high-performance ASICs. Collaborate with RTL designers to ensure design feasibility and manufacturability. Utilize EDA tools for physical design tasks such as Cadence, Synopsys, or Mentor Graphics. Conduct DRC/LVS checks and ensure design compliance with specifications. Support the verification team in physical design verification activities. Participate in design reviews and provide feedback for design improvements. Skills and Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 2-7 years of experience in ASIC physical design or related roles. Strong knowledge of ASIC design flow and methodologies. Proficiency in using EDA tools for physical design (e.g., Cadence, Synopsys, Mentor Graphics). Experience with place and route, timing closure, DRC/LVS checks, and physical verification. Familiarity with scripting languages (e.g., Perl, Tcl, Python) for automation of design tasks. Understanding of semiconductor manufacturing processes and design for manufacturability (DFM). Strong problem-solving skills and attention to detail.

What You ll Be Doing: Manage and lead a team of 7-8 SoC/Subsystem RTL Design Engineers for various customer engagements. Work with Synopsys customers to understand their needs and define RTL Signoff and design scope and activities. Lead the team to perform various RTL Design and Signoff activities for SoC Subsystems such as SoC u-Architecture and Integration, RTL Design (Verilog/SystemVerilog), Lint, CDC, RDC, Synthesis, Constraints Development. Assist and mentor the team in day-to-day activities and grow the capabilities of the RTL Design team for future assignments. Review various results and reports to provide continuous feedback to the team and improve the quality of deliverables. Report status to management and provide suggestions to resolve any issues that may impact execution. Understand the complexity and requirements of RTL Quality Signoff and propose resource requirements to complete the activities. Work with peers to improve methodology and improve execution efficiency. Collaborate with other Synopsys teams including BU AEs and Sales to develop, broaden and deploy Tools. Train the team in design concepts and root-cause analysis. The Impact You Will Have: Drive the successful delivery of SoC Subsystems by leading a skilled team of RTL Design Engineers. Enhance the quality and efficiency of RTL Design and Signoff processes through continuous feedback and methodology improvements. Ensure customer satisfaction by understanding their needs and delivering high-quality solutions. Contribute to the growth and development of the RTL Design team, expanding their capabilities for future projects. Support Synopsys reputation as a leader in chip design and verification through successful project execution. Foster collaboration and innovation within the team and across different Synopsys departments. What You ll Need: B.E/B. Tech/M.E/M. Tech in electronics with a minimum of 12+ years experience in SoC RTL Design. Technical expertise in various aspects of RTL Design and Signoff: LINT, CDC, RDC. Technical expertise on setting up flows and methodologies for quick deployment of RTL Signoff tools. Technical expertise in debugging and diagnosing violations and errors. Technical expertise in developing timing constraints and running preliminary synthesis for timing constraints check and area estimation. Ability to lead and manage a team to perform RTL Signoff on complex SoC/Subsystem. Experience with planning and managing various activities related to RTL Signoff and Design. Strong understanding of design concepts, ASIC flows, and stakeholders. Good communication skills. Who You Are: A proactive leader with excellent managerial skills. A team player who can mentor and guide engineers. An effective communicator who can interact with customers and stakeholders. A problem-solver with a keen eye for detail. An innovator who continuously seeks to improve processes.

Description We are seeking a Staff ASIC RTL Digital Design Engineer to join our dynamic team in India. The ideal candidate will have a strong background in ASIC design and will be responsible for developing high-quality RTL designs, participating in verification processes, and collaborating with multiple teams to ensure successful project completion. Responsibilities Design and implement RTL code for ASIC digital circuits. Perform RTL simulations and verification using tools like ModelSim or VCS. Collaborate with verification engineers to ensure design functionality and performance. Participate in design reviews and provide constructive feedback. Work closely with physical design teams to ensure successful handoff and integration of digital designs. Troubleshoot and resolve design issues during the development and testing phases. Skills and Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 5-10 years of experience in ASIC digital design and RTL coding. Proficient in VHDL/Verilog/SystemVerilog for RTL design. Experience with digital design tools such as Cadence, Synopsys, or Mentor Graphics. Strong understanding of digital logic design principles and methodologies. Familiarity with ASIC design flow, including synthesis, place and route, and timing closure. Ability to work collaboratively in a team environment and communicate effectively with cross-functional teams.

Working on Functional Verification of High-Speed PHY IPs for DDRxx, LPDDRxx, PCIex, Display, and HDMI protocol standards. Studying IP/design blocks/Firmware Specifications and building/updating verification plans and test cases. Building/updating functional verification environments to execute test plans. Developing DV/Firmware test benches, test plans, and test cases. Implementing checkers, assertions, random test generators, high-level transactional models, and bus functional models (BFMs). Performing simulation, random and focused stimulus generation, and coverage analysis. Collaborating closely with digital designers for debugging and achieving desired coverage. Developing architecture and micro-architecture knowledge of complex digital design blocks under test. The Impact You Will Have: Ensuring the high quality and reliability of our High-Speed PHY IPs. Contributing to the successful delivery of cutting-edge technology solutions. Enhancing the performance and functionality of our products through rigorous verification. Driving innovation and excellence in our verification processes. Supporting the rapid integration of capabilities into SoC designs. Enabling our customers to bring differentiated products to market quickly with reduced risk. What You'll Need: B. Tech/M. Tech in EC/CS with 3-6 years of relevant experience in pre-silicon verification of complex PHY IPs, ASIC, or SoC designs. Understanding of functional verification flow with experience on industry-standard development and verification tools and methodologies such as VMM, OVM/UVM, and System Verilog. Proficiency in System Verilog Assertions, code and functional coverage implementation, and review. Excellent debug and diagnostic skills. Experience with scripting and automation using TCL, PERL, or Python.

We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are an experienced and motivated SOC Engineer with a passion for cutting-edge technology and innovation With a strong background in system-on-chip (SOC) design and verification, you bring a wealth of knowledge and a keen eye for detail You thrive in a collaborative environment, working seamlessly with cross-functional teams to deliver high-quality solutions Your problem-solving skills are exceptional, and you have a proven track record of successfully managing complex projects You are proactive, adaptable, and always eager to learn and grow in a dynamic and fast-paced setting, What Youll Be Doing: Designing and implementing SOC solutions for various applications, ensuring high performance and reliability, Collaborating with cross-functional teams to define and develop SOC architecture and specifications, Conducting verification and validation of SOC designs to ensure compliance with industry standards and customer requirements, Optimizing SOC designs for power, performance, and area (PPA) to meet project objectives, Debugging and resolving issues in SOC designs, utilizing advanced tools and methodologies, Providing technical guidance and mentorship to junior engineers, fostering a culture of continuous improvement and innovation, Job Description And Requirements The role is for RTL Design and Signoff of IP/Subsystem/SoC Design in the System Solutions Group (SSG) At SSG, we are a team of experts in various Synopsys technologies to deliver architecture, design, verification, implementation, tools, methodology to enable our customers complete their most challenging SoC Design projects Our work spans from sub-blocks to full turnkey end-to-end SoCs Our customers range from start-ups to industry leaders, commercial companies, and government agencies, As part of this role, you can expect to develop and deliver your expertise in RTL Signoff and RTL Design Techniques while working on activities such as Lint/CDC/RDC Checks, Timing Constraints Development, Preliminary Synthesis, Formality and RTL Design The role will expose you to various innovative technologies deployed for RTL Quality Signoff for Semiconductors, Responsibilities Perform RTL Quality Signoff Checks such as LINT, CDC, RDC, Understand the design/architecture and develop timing constraints for synthesis and timing, Run preliminary synthesis to ensure that the design can be synthesized as intended, Run formality to ensure equivalence of RTL and gates, Integrate IPs in SoCs/Subsystems and create RTL design as per need of the customer, Required E/B Hands-on experience on static verification tools such as Spyglass performing LINT, CDC, RDC, Good conceptual understanding of design/architecture pitfalls across clock/reset domain crossing, Good conceptual understanding of RTL rule checks, Hands-on experience on synthesis and timing constraints development, Candidates with experience on ARM based technologies (Coresight Debug, Processor architecture, etc ) will be preferred, The Team Youll Be A Part Of: You will join a highly skilled and motivated team dedicated to developing advanced SOC solutions Our team focuses on innovation, collaboration, and excellence, working together to deliver high-quality designs that drive technological advancements We value diversity and inclusion, fostering a supportive and dynamic environment where every team member can thrive and contribute to our success, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring proces

What You ll Need: MS/Ph.D. in Computer Science, Computer Engineering, or Electrical Engineering. 15+ years of experience in software development and testing large C++ applications in Linux. Expertise in RTL Simulation andemulation/prototyping. Ability to understand and solve complex technical problems. Experience with runtime performance improvements and benchmarking.

We are looking for a passionate and self-driven individual to join the NES SOC architecture team and to help define and build NEX SoC(s) for Intel Server, Client and IoT platforms.Your responsibilities will include, but are not limited to:definition, specification and analysis of a family of Interconnects for use with Intel and ARM architecture based SoC(s).- Analysis of IP bandwidth, latency requirements and define SOC Coherent and Non-coherent interconnect.- define interconnect topology- Analysis of workloads and partitioning to determine candidates for coherent and non-coherent interconnect choices.- Performance modeling and Analysis Qualifications: Behavioral traits that we are looking for: Strong problem solving, debugging, multi-tasking, and brainstorming skills Ability to collaborate, be inclusive, and influence across a diverse cross-organizational team Ability to analyze the solution for various pros/cons Work will include a combination of individual contribution and leveraging team participation through mentoring and leadership of technical initiatives. Minimum Qualifications: A bachelor's degree in Electrical/Electronics Engineering or related field with 12+ years of experience. Or a master's degree with 10+ years of experience. Job Type: Experienced Hire Shift: Shift 1 (India)