1323 Rtl Design Jobs - Page 17

General Summary: Senior/Lead ASIC Verification Engineers with an experience of minimum 5+ yrs Very strong experience with Verilog, System Verilog and UVM Working experience on development of Verification IP of layered protocol High Speed peripheral Interface protocol PCIe Gen4+ onwards, PCIe Experience is a must Strong knowledge on UVM RAL and common register interfaces such as APB, AHB, AXI (ARM), RAM. Working experience on scripting and automation Strong Past experience of developing verification plan from scratch and testbench development using the detailed Specification and TestPlan from the scratch Strong base knowledge on digital design, blocks/components Strong debugging skills and Go...

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer ...

In this job you will be responsible for specifying and/or micro-architecting digital blocks in advanced mixed-signal circuits. You will be also responsible for RTL coding of blocks specified by you or others. You will participate in the design verification and bring-up of such blocks by writing meaningful assertions, debugging code, and otherwise interacting with the design verification team. Requirements: Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. 4 to 10 years of experience in RTL designs. Deep knowledge of mixed signal concepts Deep knowledge of RTL design fundamentals Deep knowledge of Verilog and System-Verilog Deep knowledge of front-...

Role: RTL Design Engineer Experience: 10+years Notice Period: Max 15days preferred Role Overview We are looking for a RTL Design Engineer? to deploy andsupport our front-end tools, to develop scripts to automate regression anddebug flows, and to work along with our design, implementation and verificationteams. What you'll do Deploy and support front-end tools, such as, RTL simulators, low power tools, static RTL checkers such as Lint, CDC/RDC/SDC/DFT, and formal verification. Develop scripts to automate regression and debug flows, and to enable Continuous Integration/Continuous Delivery (CI/CD) Streamline utilization of compute infrastructure using load distribution tools Identify and priori...

As a successful candidate for this role, you should possess a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or have equivalent practical experience. You should have at least 10 years of experience in Camera ISP image processing or other multimedia IPs like Display or Video Codec. Additionally, you should have a solid background with System Verilog Assertions (SVA), assertion-based verification, and formal verification, with at least 4 years of experience in people management and employee development. Preferred qualifications for this position include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Compute...

As a Design and Verification Trainer, you will be responsible for providing guidance and support to budding engineers in the areas of RTL design, functional verification, and VLSI concepts. Your practical experience in front-end design and verification methodologies will be crucial in effectively conveying technical knowledge in an organized, engaging, and articulate manner. Key Responsibilities: - Utilize your strong command over hardware description languages such as Verilog and SystemVerilog - Demonstrate a deep understanding of verification methodologies including UVM and SystemVerilog Assertions - Proficiency in simulation and debugging tools like Synopsys VCS, VERDI, and Spyglass - Emp...

As a PHY Hardening Engineer at Ampere, you will have a crucial role in developing cutting-edge expertise in high-speed digital design. You will collaborate with various teams, including architects, RTL designers, packaging and PCB design teams, and post-silicon validation groups. Your tasks will involve optimizing layouts, ensuring signal and power integrity, and performing chip-level physical design tasks. Your expertise in managing high-speed signals and advanced packaging techniques will be vital in delivering reliable designs meeting timing, power, and manufacturability requirements. Key Responsibilities: - Collaborate with cross-functional teams to optimize layouts and ensure signal and...

Synthesis & STA Engineers: Synthesis & STA engineers will perform RTL Synthesis to achieve the best Performance/ Power/ Area of the designs, DFT insertions that include MBIST and SCAN, setup Timing Constraints for functional and Test Modes, and Validation. Proven hands-on experience on Design compiler/ Genus/ Fusioncompiler Experience timing analysis/debug and driving the timing convergence for complex blocks and release the netlists to PD team Ability to own and release the complex blocks from RTL to netlist with timing QOR, CLP cleanup, Check timing, DFT constraint integration. Ability to work with RTL design team to identify the must changes in RTL to coverge the timing and work with PD t...

Summary: Own end-to-end RTL design for complex SoC or large subsystem blocks, from micro-architecture through tapeout and silicon bring-up. Responsibilities: Define micro-architecture from specs; write high-quality synthesizable SystemVerilog/Verilog RTL for SoC-level or large subsystems. Own design bring-up, block/subsystem integration, and close on timing, power, and area with synthesis and PnR teams. Drive design reviews, close bugs, and support silicon validation and post-silicon debug. Collaborate with DV to define test plans, assertions, and coverage goals; support emulation/FPGA only as a secondary validation aid (not counted toward the 8 years). Must-have qualifications: 8+ years of ...

Overview Please refer JD Responsibilities Please refer JD Qualifications Please refer JD

Job Specs : Expertise in ASIC RTL Design Expertise in ASIC IP Design Expertise in CDC and Lint tools Expertise in design and simulation tools Expertise in Video processing algorithms / interfaces Expertise in CXL / PCIe Protocol, 5G, Datacenter Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Vietnam are the preferred work locations Preferred resources with valid regional work permit.

We are looking for a passionate and experienced EDA Methodology Engineer to join our ASICdesign team, focusing on Spyglass lint checking using Synopsys Spyglass for CDC/RDC. In this role, you’ll work closely with design teams and EDA vendors to develop and implement robust verification flows that ensure structural correctness across design stages Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Bachelor’s or Master’s degree in Computer Science, Electronics Engineering, or VLSIDesign. 5–8 years of hands-on experience with Synopsys Spyglass. Strong understanding of RTL design languages: VHDL, Verilog, SystemVerilog. Expertis...

Role & Responsibilities : Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Required Professional and Technical Expertise : 3-8 years of experience in Design Verification - demonstra...

About The Role This role involves the development and application of engineering practice and knowledge in the following technologiesElectronic logic programs (FPGA, ASICs); Design layout and verification of integrated circuits (ICs),printed circuit boards(PCBs), and electronic systems; and developing and designing methods of using electrical power and electronic equipment; About The Role - Grade Specific Focus on Electrical, Electronics and Semiconductor. Develops competency in own area of expertise. Shares expertise and provides guidance and support to others. Interprets clients needs. Completes own role independently or with minimum supervision. Identifies problems and relevant issues in ...

Desired Profile : B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Engineering. Expertise in mixed signal IC verification / design experience Expertise in analog and mixed-signal circuit topologies Define verification plan based on product specifications and application use-cases Develop top-level AMS test benches using Cadence / System Verilog / UVM framework Simulate and validate verification plan use-cases Work with design team to debug and support issues Manage bug tracking Create automated regression flows Document and organize regression results Conduct AMS waveform review master the full AMS verification process. Expert level proficiency (Oral + Written) in Chinese langu...

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

Work with design and architecture teams to define and generate timing constraints that specify the desired timing requirements for the design. Set up and configure STA tools (e.g., Cadence Encounter, Synopsys PrimeTime) for the analysis, including library characterization, delay models, and clock definitions. Perform static timing analysis to evaluate setup and hold times, clock-to-q delays, and other timing metrics. Ensure that the design meets timing requirements for various corners and operating conditions (e.g., process, voltage, temperature variations). Identify and analyze asynchronous signals crossing between different clock domains to ensure proper synchronization and to avoid metast...

Job Description: This is a full-time role for an FPGA Design Engineer at Agiliad Technologies in Pune. The FPGA Design Engineer will be responsible for tasks related to designing and developing products using Lattice and Altera FPGAs. Collaborating with cross-functional teams on product development. Job Title: FPGA Design Engineer Location: Pune Experience level: 4 -6 Years Responsibilities and Skills: In depth knowledge with VHDL/Verilog/System Verilog, Embedded C, RTL design, FPGA design, Knowledgeable about FPGA architecture. In-depth tool flow knowledge of FPGA design tools any of Xilinx, Altera, Lattice. Must be willing to learn new software tools. Complete FPGA development flow from lo...

As a Qualcomm Hardware Engineer, your role involves planning, designing, optimizing, verifying, and testing electronic systems to launch cutting-edge, world-class products. You will collaborate with cross-functional teams to develop solutions and meet performance requirements. **Key Responsibilities:** - Front-End implementation of MSIP (Temp/Voltage/Security Sensors, Controllers) designs - RTL development and its validation for linting, clock-domain crossing, conformal low power, and DFT rules - Work with functional verification team on test plan development and debug - Develop timing constraints, deliver synthesized netlist to physical design team, and provide constraints support for PD ST...

As an RTL Designer in DSP Processor Team at Qualcomm India Private Limited, you will be responsible for developing RTL for multiple logic blocks of a DSP core. Your role will involve running various frontend tools to check for linting, clock domain crossing, synthesis, etc. You will collaborate with the physical design team on design constraints and timing closure, work with the power team on power optimization, and coordinate with the verification team on test plan, coverage plan, and coverage closure. Key Responsibilities: - Develop RTL for multiple logic blocks of a DSP core - Run various frontend tools to check for linting, clock domain crossing, synthesis, etc. - Collaborate with the ph...

Skill-RTL Experience =5-15 years Location-Bangalore/Hyderabad

Infinera is now part of the Nokia Corporation and its subsidiaries. When you apply, the information you share will be handled with care and used only for recruitment purposes within the group.As an FPGA Verification engineer, you will be responsible for designing verification plans, developing environment/testbench, creating test scenarios for running simulations, coverage analysis and lab support during board bring up to ensure first time right quality of Infinera product. Candidate should be capable of handling projects independently and have a strong will to drive for solutions. Must have 12-16 yearsof experience in developing System Verilog UVM based test environments, developing and imp...

Required skills: He/She should be able to do top-level floor planning, PG Planning, partitioning,placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. He/She should have worked on 65nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. Provide technical guidance, mentoring to physical design engrs. Interface with front-end ASIC teams to resolve issues. Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques. Timing...

About The Role Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Design for Testability (DFT) Good to have skills : NAMinimum 15 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your typical day will involve collaborating with various teams to ensure that application requirements are met, overseeing the development process, and providing guidance to team members. You will also engag...