1323 Rtl Design Jobs - Page 15

As a member of the Front End CAD team, you will be responsible for the development, standardization and maintenance of engineering flows that enable system verification activities within the Solutions Engineering team, working with engineers from our project teams to help them deploy best-practise across a common set of requirements. The flows you will help to develop will include areas such as simulation, emulation and formal verification and advancements in machine-readable specifications to aid automation of standard methodology within SE, enabling our verification community to achieve the best possible results. You will collect and analyse verification metrics and work with tools from mu...

We are seeking an experienced and highly skilled Senior SOC Design for Test Engineer with aminimum of 5 years of hands-on experience in SOC Design for Test. As a key member of our team, you will play a pivotal role in ensuring the testability, manufacturability, and quality of our cutting-edge System on Chip designs Key Responsibilities Lead and manage SOC Design for Test efforts for complex projects, ensuring the successful execution coverage, manufacturability, and quality plans. Develop full chip and block level DFT implementation from the DFx Specifications and product coverage, quality, and manufacturability goals. Define and implement Test controllers at top level and block level, fuse...

As an experienced RTL Micro Architect at Eximietas Design, you will be a key contributor in defining and implementing cutting-edge semiconductor designs. Your role will involve working on complex RTL design challenges, collaborating with cross-functional teams, and delivering high-performance, power-efficient, and innovative solutions. Key Responsibilities: - Define and develop microarchitecture specifications for complex SoC designs. - Lead RTL design and implementation using Verilog/System Verilog, ensuring optimal performance, power, and area (PPA). - Collaborate with system architects, verification teams, and physical design teams for successful project execution. - Perform design trade-...

Designation: Member Technical Staff No.of positions : Multiple Experience : 3- 15 Years Education : MTech VLSI / BE. ECE Industry Type : Education / E-Learning / Semiconductor Functional Area : Training category: Technical Filter: Full- time Job Description Extensive hands on and teaching experience on Digital / SV /UVM/ Verilog / Analog /DFT tools Extensive experience in Back-end design Experience on Mentor Graphics EDA flow is an added advantage Responsible for development and support of Projects. Responsible for Debugging the source codes in Verilog, SV, and UVM. Responsible for Training Delivery and Support Desired Candidate Profile Sound Knowledge on Digital / Verilog / Analog / SV / UV...

We are seeking an exceptional Senior Physical Design Engineer to take a key role in our semiconductor design team. As a Senior Physical Design Engineer, you will lead the development and implementation of cutting-edge physical design methodologies and flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensure the successful delivery of high-quality designs Key Responsibilities Perform Synthesis, floor planning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs. Define and drive physical design strategies to meet aggressive performance, power, and area targets. Conduct detailed analysis of timing, power, and area, and drive de...

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

- Should have worked hands-on ASIC DFT design, implementation, vector generation/verification, JTAG, boundary scan and simulation. -Experience with Scan, Compression, ATPG and simulations with Mentor/Synopsys/Cadence tools. Logic BIST knowledge is a plus. - Should have participated in successful tapeouts ofSoC/ASIC chips at Lower nodes ; 14nm or below and achieved test targets. - Descent understanding of front-end SoC/ASIC design and implementation including Synthesis and STA. -Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process -Excellent problem solving and debugging skills. Proactive in nature - Excellent Customer interaction, Communication and Team w...

We are seeking an exceptional STA Engineer to take a key role in our semiconductor designteam. As STA Engineer you will get opportunity to work with talented and passionate STAengineers and create designs that push the envelope on performance, energy efficiency andscalability. you will lead the STA for cutting-edge high speed and complex large ASIC. Youwill collaborate closely with cross-functional teams to ensure the successful delivery of highquality designs Responsibilities: Responsible for leading a team of STA engineers and close high frequency, lower tech node complex designs. Understand Design Architecture and timing requirements Develop timing constraints SDC and validate Work with ...

You have a job opportunity for the Manager / Senior Role Physical Design Engineer position in Hyderabad. Your primary responsibilities will include: - Performing IP/Block level PnR activities from Netlist to GDS-II - Demonstrating good knowledge of all PnR activities such as Floor-planning, Placement, CTS, Routing, Timing closure (STA), and signoff checks like FEV, VCLP, EMIR, and PV - Executing all the Physical Implementation steps from Physical Synthesis to a Sign-Off GSD2 file - Handling signoff convergence, block-level Timing Signoff, ECO generation, and Power signoff - Having knowledge of high performance and low power implementation methods (preferred) - Expertise in ICC2/Fusion Compil...

Minimum qualifications: Bachelors degree in Electrical/Computer Engineering or equivalent practical experience 3 years of experience with Register-Transfer Level (RTL) design and integration using Verilog/System Verilog, microarchitecture and automation Experience with RTL design using Verilog/System Verilog and microarchitecture Experience with a scripting language like Python or Perl Preferred qualifications: Master's degree in Computer Science or Electrical Engineering 6 years of industry experience with IP design Experience with methodologies for low power estimation, timing closure, and synthesis Experience with methodologies for RTL quality checks (e-g , Lint, CDC, RDC) About the jobBe...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performanc...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performanc...

About The Role Your Role As a SoC GLS Verification Engineer , you will play a key role in verifying complex SoC designs through Gate-Level Simulation (GLS). You will work closely with design and verification teams to ensure functional correctness, timing accuracy, and overall quality of silicon-ready designs. Your expertise in GLS methodologies and debugging will be critical in delivering high-performance, reliable SoCs. In this role, you will: Perform GLS using Zero Delay , SDF , and Post-Layout GLS (PAGLS) techniques. Debug and resolve issues in gate-level simulations to ensure timing and functional correctness. Develop and maintain SystemVerilog/UVM testbenches for GLS environments. Colla...

About The Role This role involves the development and application of engineering practice and knowledge in the following technologiesElectronic logic programs (FPGA, ASICs); Design layout and verification of integrated circuits (ICs),printed circuit boards(PCBs), and electronic systems; and developing and designing methods of using electrical power and electronic equipment; About The Role - Grade Specific Focus on Electrical, Electronics and Semiconductor. Develops competency in own area of expertise. Shares expertise and provides guidance and support to others. Interprets clients needs. Completes own role independently or with minimum supervision. Identifies problems and relevant issues in ...

Develop and maintain formal equivalence checking flows using Synopsys Formality. Collaborate with cross-functional teams to align verification methodology with design goals. Implement and support Formality ECO flows for incremental synthesis. Drive methodology improvements for SoC design verification. Coordinate with internal stakeholders and external vendors to deliver high-quality solutions. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Bachelor’s or Master’s degree in Computer Science, Electronics Engineering, or VLSI Design. 5–8 years of hands-on experience with Synopsys Formality or similar tools (e.g., Cadence Con...

RTL Design Engineer Job Title: RTL Design Engineer Location: [Bangalore / Hyderabad / Noida / Chennai / Pune] Experience: 03 years Education: B.E/B.Tech or M.Tech in ECE, EE, or VLSI Responsibilities: Develop RTL code in Verilog/System Verilog for digital IPs or SoCs Implement and integrate IPs based on specifications Ensure quality RTL that is synthesizable and meets timing Support verification and debug efforts during simulation and emulation Participate in code reviews and design documentation Requirements: Strong fundamentals in digital logic and computer architecture Experience with Verilog/System Verilog Exposure to synthesis tools and Lint/CDC checks Familiarity with scripting (Perl, ...

Role & responsibilities Please share me interested candidate cv galeiah.g@honeybeetechsolutions.com Position Name RTL Engineer Position type: Permanent Total Exp: 5+ years HBTS Budget: Open Notice Period: Immediate 15DAYS Work Location: Hyderabad Job Description Must have: 1. At least 5yrs of industry experience 2. Experience with RTL frontend tools like RDC, CDC, Lint etc 3. Experience with writing and validating synthesis constraints. 4. Experience with scripting like perl, python, tcl etc. Preferred candidate profile

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned engineering professional with a passion for tackling complex SoC challenges. With 12+ years experience, you thrive in dynamic environments and excel at leading multidisciplinary teams through the intricacies of RTL design and signoff. You possess deep expertise ...

Alternate Job Titles: RTL Design Supervisor Digital Design Team Lead High-Speed Protocols Supervisor ASIC Design Supervisor We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are highly collaborative, valuing knowledge sharing and contributing to a culture of continuous improvement. Your familiarity with protocols like USB ena...

You are seeking an experienced ASIC SOC RTL Design Engineer/Lead to join the dynamic team at Eximietas Design in Bengaluru. As a key contributor, you will be pivotal in defining and implementing cutting-edge semiconductor designs, focusing on high-performance, power-efficient, and innovative solutions. Key Responsibilities: - Define and develop microarchitecture specifications for complex SoC designs. - Lead RTL design and implementation using Verilog/SystemVerilog, optimizing performance, power, and area (PPA). - Collaborate with cross-functional teams to ensure successful project execution. - Conduct design trade-off analysis to meet functional, performance, and power requirements. - Devel...

Candidate will be responsible for building/maintaining highlyconfigurable and reusable IO Subsystems (Note: An IO Subsystem is alogic IP that processes the IO Pads/IO Ring information and requiredlogic to allow multiple on-chip peripherals to share the same IOs in aconfigurable manner) Job Description In your new role you will: Candidate will be responsible for building/maintaining highly configurable and reusable IO Subsystems (Note: An IO Subsystem is a logic IP that processes the IO Pads/IO Ring information and required logic to allow multiple on-chip peripherals to share the same IOs in a configurable manner) Candidate will be responsible for RTL design for integration of IO pads into So...

As Logic deisgn engineer for Power Management, you will be responsible for design and development of power management and sustainability features for high performance Processors chips. 1. Lead the Development of features - propose enhancements to existing features, new features, architecture in High level design discussions 2. Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW, Research teams to develop the feature 3. Guide junior engineers. Represent as Power engineer in various forums. 4. Signoff the Pre-silicon Design that meets all the functional, area and timing goals 5. Participate in silicon bring-up and validation of the hardwar 6....

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-8 years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC ver...

Role Purpose The purpose of the role is to design, and architect VLSI and Hardware based products and enable delivery teams to provide exceptional client engagement and satisfaction. Do Define product requirements, design and implement VLSI and HARDWARE Devices. Constant upgrade and updates of design tools, frameworks and understand the analysis of toolset chain for development of hardware products. Ability to analyse right components and hardware elements to choose for product engineering or development. Ability to conduct cost-benefit analysis and choose the best fit design. Knowledge on end to end flow of VLSI including design, DFT and Verification and Hardware product development from de...

Roles and Responsibilities: 1. Handling request from vessel or TSI for Adding / amending /removal of PMS routines: Amendment request from vessel is sent to TSIs approval and as technical committee member same will be forwarded to PMS DB (by referring technical manuals, makers manual, makers circular). Activation of calendar-based work order while new job is added. For counter-based work order liaising with vessel and activating the same. on completion making sure amendments are reflecting in shore end as requested and intimating the same to vessel /TSI. 2. On signers briefing: For newly joining officers briefing on Shippalm v3 for all 5 modules provide on daily basis via MS teams and physica...