RTL Design Engineer

Job Description

We are looking for professionals with hands-on expertise in: ✔ RTL design from scratch (Verilog) ✔ SoC integration and logic optimization ✔ Synthesis using Vivado, Synopsys DC, or Cadence Genesis ✔ STA, CDC, Linting, and constraints development ✔ Protocols: AXI, AHB, APB, TileLink, PCIe, DDR ✔ Collaboration with verification and physical design teams Mandatory Skills for RTL Design Engineer: Strong RTL design skills using Verilog Experience in SoC integration Proficiency in RTL synthesis tools such as Vivado, Synopsys DC, or Cadence Genesis Expertise in Static Timing Analysis (STA), Clock Domain Crossing (CDC), and Linting Ability to create and update constraint files Working knowledge of protocols like AXI, AHB, APB, TileLink, PCIe, DDR Collaborative experience with verification and physical design teams Bonus: Experience with Tapout flow is an added advantage. This Job is also avalabie in these Locations. Locations: Gurgaon | Bangalore | Pune Job Types: Full-time, Permanent Pay: ₹1,300,000.00 - ₹1,700,000.00 per year Benefits: Flexible schedule Work Location: In person