RFIC Layout Engineer

As an RFIC/MMIC Layout Engineer, your role involves designing, planning, scheduling, and executing Full Chip development with analog and digital components. You will be responsible for performing Full chip feasibility and die size estimation, expertise in floorplan, power schemes, Interface signal planning and routing, physical verification, and quality check. It is crucial to deliver quality full chip layout on-schedule meeting design intent including Speed, Capacitance, Resistance, Power, Noise, and Area. You will work on complex issues, exercise judgement in selecting methods, and build strong business relationships with cross-functional teams for project execution. Working closely with Synaptic Global Analog and Digital Design and CAD engineering teams is an essential part of your responsibilities. Key Responsibilities: - Design, plan, schedule, and execute Full Chip development with analog and digital components - Perform Full chip feasibility and die size estimation for different bonding schemes - Expertise in floorplan, power schemes, Interface signal planning and routing, physical verification, and quality check - Ensure quality full chip layout delivery meeting design intent criteria - Resolve complex issues and exercise judgement in method selection - Build strong business relationships with cross-functional teams - Collaborate with Synaptic Global Analog and Digital Design and CAD engineering teams Qualifications Required: - Bachelors degree in electrical engineering, Electronics, Physics, or related field - Experience in RF and MMIC design with expertise in RF switches, power amplifiers, LNA, VCO, mixers, couplers, combiners layout Additional Company Details: The preferred skills and experience for this role include a good understanding of active and passive devices, circuits, and electrical fundamentals. Expertise in CMOS, FDSOI, and FinFET fabrication concepts, as well as analog layout techniques, electromigration, ESD, latch up, crosstalk, shielding, and deep sub-micron challenges, is desired. Hands-on experience with Virtuoso L/XL/GXL, Calibre, PERC, STARRC, Totem, and ESRA tools is preferred. Strong analytical, debug, and problem-solving skills are essential for resolving layout design challenges and physical verification issues. Being flexible to work in a cross-functional and multi-site team environment, spanning different time zones, and possessing good verbal and written communication skills are important for this role.,