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3.0 - 7.0 years

0 Lacs

karnataka

On-site

As an RFIC/MMIC Layout Engineer, your role involves designing, planning, scheduling, and executing Full Chip development with analog and digital components. You will be responsible for performing Full chip feasibility and die size estimation, expertise in floorplan, power schemes, Interface signal planning and routing, physical verification, and quality check. It is crucial to deliver quality full chip layout on-schedule meeting design intent including Speed, Capacitance, Resistance, Power, Noise, and Area. You will work on complex issues, exercise judgement in selecting methods, and build strong business relationships with cross-functional teams for project execution. Working closely with S...

Posted 1 week ago

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4.0 - 8.0 years

0 Lacs

karnataka

On-site

As an IO Layout Engineer at our company, you will play a crucial role in the layout design of IO blocks such as GPIO, Analog IOs, High-Speed IOs, and Pad ring. Your responsibilities will include: - Working on IO layout for ASIC controllers under the guidance of senior team members. - Collaborating closely with designers to understand design constraints and create quality layout efficiently. - Managing all the Sign Off PV & quality checks on an IP layout. To excel in this role, you are required to meet the following qualifications and requirements: - Hold a Bachelor's or Master's degree in Electronics & Communication/Electrical engineering. - Possess 4 to 8 years of working experience in IO l...

Posted 1 week ago

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3.0 - 10.0 years

0 Lacs

bengaluru, karnataka, india

On-site

Job Requirements Bachelor's or master's Degree with 3-10 years of Analog Layout experience. Good understanding of advanced semiconductor technology process and device physics. Full-custom circuit layout/verification and RC extraction experience. Experience in one or more of the following areas is preferable : Mixed signal/analog/high speed layout, e.g. PLL, IO, RF, PMIC, OSC, DC-DC convertor, Temperature sensor, SRAM, TCAM, ROM, MRAM, ESD Familiar with Cadence Virtuoso environment and various industry physical verification tools (DRC,LVS,DFM, etc). Experiences in advanced technology node under 16nm/14nm/7nm. 5nm/3nm will be an added advantage. Must have expertise on Totem EMIR & Self-heating...

Posted 3 weeks ago

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5.0 - 9.0 years

0 Lacs

karnataka

On-site

As an RFIC/MMIC Layout Engineer, you will be responsible for the design, planning, scheduling, and execution of Full Chip development involving analog and digital components. Your key responsibilities will include: - Performing Full chip feasibility and die size estimation for different bonding schemes - Demonstrating expertise in floorplan design, power schemes, signal planning, routing, physical verification, and quality check - Ensuring the delivery of quality full chip layout on-schedule while meeting design intent criteria such as Speed, Capacitance, Resistance, Power, Noise, and Area - Handling complex issues and using judgment to select appropriate methods for obtaining results - Esta...

Posted 2 months ago

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