Directs and manages a team of PDK engineers focused on the quality assurance of process design kit (PDK) collateral for design (both internal and external) to enable new processes. Looking for candidate who is experienced in Custom Layout, SPICE Simulation, Physical Verification, APR expertise to drive end to end parasitic extraction tasks. Must have first-hand experience in working with industry standard EDA tools like Virtuoso, Spectre, Pegasus, Quantus RC, StarRC, ICV/IC Workbench, Fusion Compiler/ ICC2, Innovus, Calibre DRC/LVS/xact. Extraction space requires deep understanding of Technology changes at silicon level, able to interpret the FE,BE updates and drive the team to execute multiple QA checks and methodologies. Should be quick learner and help to the team to ungate the execution with thorough understanding of issues and quickly converge to solutions. Primary responsibility includes enablement of PDK Custom and ASIC extraction flows/ methodologies and test the PDK collaterals. Candidate is responsible in assuring the quality of Extraction decks by setting up various flows/methodologies driving the team members in developing required automation tasks. Should be self-driven and able to take up new tasks. Should closely interact with EDA vendors for enablement of new features / additions to the existing flows / methodologies. Provide support for internal customers, collaborate with EDA vendors for enhancement of the flows based on customer requests. Should be proficient in documenting the observations made from the flows executed. Automation of the key capabilities for design productivity is critical responsibility. Interfacing with PDK Dev teams, Cross Functional, EDA vendors, contracting employees. Oversees root cause analysis for issues related to designing to a specific process technology and drives initiatives and innovation to enhance design methodologies to develop high quality solutions and ensure ease of use for both internal and external design communities. Ensures all issues found during validation are filed in a ticketing database and ensure traction and closure before PDK release. Root causes QA misses and incoming customer issues and adds corrective actions to close gaps. Responsible for enabling teams to execute through clear goal setting, facilitating work, maintaining accountability, applying differentiated performance management, and driving team results. Drives results by inspiring people, role modeling Intel values, developing the capabilities of others, and ensuring a productive work environment. Qualifications Master's in EC or EE or CSE with 12+ yrs Exp or Bachelor's in EC or EE or CSE with 15+yrs industry experience in PDK development and QA. Experience in custom layout design methodology, ASIC physical design / PnR flow and industry standard tools for extraction (StarRC, QRC). Candidate should have good knowledge on semiconductor physics, process technology, EDA tools and associated challenges for advance technology. Candidate should be well versed with different parameters to optimize flow in terms of quality and resources. Must be proficient in automation using skill, tcl, python, perl and other scripting languages.Ability to be cognitively flexible and agile in a fast-changing software environment. Planning, prioritization, delegation skills are required. Excellent verbal and written communication is a must.
