8 - 13 years
8 - 15 Lacs
Posted:3 weeks ago|
Platform:
Work from Office
Full Time
We are looking for a highly skilled Senior RTL Design Engineer with 8+ years of experience in designing complex digital IPs and SoCs. The ideal candidate should have strong RTL coding, micro-architecture, and synthesis knowledge, with a proven track record of successful tape-outs.
Key Responsibilities:Develop RTL code in Verilog/SystemVerilog based on micro-architecture specificationsWork on design partitioning, clock domain crossings, and low-power techniquesCollaborate with verification, physical design, and DFT teams across the design cyclePerform lint, CDC, and synthesis with timing constraintsOptimize design for area, performance, and powerParticipate in design reviews and documentation
Requirements:8+ years of RTL design experience in ASIC/SoC developmentStrong knowledge of digital design principles and SoC architectureHands-on experience with RTL design tools (SpyGlass, Design Compiler, etc.)Experience with AMBA protocols (AXI, AHB, APB), FIFOs, arbiters, and bus interfacesExposure to synthesis, STA constraints, and backend handoffStrong debugging, problem-solving, and communication skills
How to Apply:If this role excites you, submit your updated resume at info@silcosys.com and any relevant project portfolios today. Join Silcosys Solutions Private Limited and shape the future.
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