2.0 - 7.0 years

5 - 12 Lacs

bengaluru

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As an RTL Design Engineer, you will be responsible for designing and implementing high-quality RTL code for complex digital blocks and subsystems. You will collaborate with architects, verification, and physical design teams to create designs that meet functional, performance, and power requirements. Responsibilities: 1. Develop RTL designs for digital IPs, subsystems, and SoCs based on architectural specifications. 2. Collaborate with architects and system engineers to translate high-level requirements into detailed micro-architecture. 3. Perform design optimizations for area, power, and performance. 4. Conduct design reviews and ensure compliance with coding standards and best practices. 5...

Posted 1 month ago

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8.0 - 13.0 years

8 - 15 Lacs

Noida, Hyderabad, Bengaluru

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We are looking for a highly skilled Senior RTL Design Engineer with 8+ years of experience in designing complex digital IPs and SoCs. The ideal candidate should have strong RTL coding, micro-architecture, and synthesis knowledge, with a proven track record of successful tape-outs. Key Responsibilities: Develop RTL code in Verilog/SystemVerilog based on micro-architecture specifications Work on design partitioning, clock domain crossings, and low-power techniques Collaborate with verification, physical design, and DFT teams across the design cycle Perform lint, CDC, and synthesis with timing constraints Optimize design for area, performance, and power Participate in design reviews and documen...

Posted 2 months ago

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RTL Engineer TekWissen

4.0 - 6.0 years

0 Lacs

Hyderabad

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Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: RTL Engineer Location:Hyderabad Work Type: Onsite Job Type: Full time Job Description: RTL coding knowledge Top-level (SOC) level basic industry standard Arch knowledge SoC & IP level Integration knowledge IPXACT knowledge IORING and Phys & GPIOs basic functionality Design Partitioning(Tilification) knowledge Design RTL quality checks: Clock domain crossing(CDC) Reset domain crossing(RDC) LINT VSI UPF knowledge LEC(Logic equivalence check) Timing concepts & SDC knowledge Tools knowledge: Vc_static or equivalent other tools(VSI) VC_spyglass LINT, CDC and RDC 0in Form...

Posted 3 months ago

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2.0 - 7.0 years

5 - 12 Lacs

Bengaluru

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Posted 3 months ago

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