Principal Design Engineer

Role Overview: You will be responsible for design and verification engineering at Cadence, where you will have the opportunity to work on complex designs and lead projects from concept to verification closure. Your role will involve utilizing your strong background in functional verification fundamentals, environment planning, and test plan generation to make an impact on the world of technology. Key Responsibilities: - Utilize your 8+ years of Design Verification experience with SV/UVM to verify complex designs - Lead projects from concept to verification closure - Develop functional verification environments using strong hands-on UVM and System Verilog coding experience - Prioritize IP verification of memory IP (DDR/HBM/GDDR) as an added advantage Qualifications Required: - BE/BTech/ME/MTech degree in Electrical/Electronics/VLSI - Experience as a design and verification engineer - Strong background in functional verification fundamentals - Proficiency in environment planning, test plan generation, and environment development - Prior experience in IP verification of memory IP would be beneficial Additional Company Details: At Cadence, we are committed to doing work that matters and solving challenges that others cannot. Join us in making an impact on the world of technology.,