Principal Design Engineer

Role Overview: Cadence is a pivotal leader in electronic design, leveraging over 30 years of computational software expertise to deliver innovative software, hardware, and IP solutions. As a part of the team working on cutting-edge technology, you will have the opportunity to contribute to the development of high-performance physical IP for industry-standard protocols. You will work in a collaborative environment that encourages creativity and innovation while ensuring project completion within set timelines and high quality standards. Key Responsibilities: - Develop digital architecture, RTL implementation, low power design, synthesis, and timing analysis for all IPs in the SerDes physical IP portfolio - Collaborate with design architects, digital verification, project management, and digital/analog design teams across multiple global locations - Drive architecture to micro-architecture to RTL implementation, refining features and requirements throughout the design process - Work with the verification team to specify coverage points, testing strategy, corner conditions, and stimulus creation - Familiarity with uC-based subsystems and their architecture - Debug verification test cases/SVAs to cover the design - Scripting of design automation - Knowledge of existing Serial standards such as PCIE, USB, Ethernet, etc. - Interaction across the IPG development team including mixed-signal, verification, and analog teams - Knowledge of multiple programming languages (System Verilog, Python, C/C++) is a plus - Working knowledge of revision control tools like Perforce, Git, SVN is a plus Qualification Required: - 7+ years of experience in Digital Design and Architecture - Good written and verbal cross-functional communication skills - Bachelor's Degree (MSEE Preferred) - Proven experience in Design Architecture, Design implementation, Embedded uC Designs, Synthesis and SDC Creation - Must be comfortable collaborating with different teams and working independently when necessary (Note: Any additional details about the company were not present in the provided job description),