9 Rtl Implementation Jobs

As an experienced ASIC/FPGA digital designer with 7-10 years of experience, you will be responsible for the following key responsibilities: - Utilize your expertise in Verilog/VHDL, Micro-architecture, and RTL Implementation to contribute to the development of cutting-edge technology. - Apply your knowledge in USB, PCIe, and Ethernet domains to design and implement efficient solutions. - Utilize tools such as Synopsys/Cadence Synthesis/STA tools and FPGA to optimize performance and functionality. - Proficiency in scripting skills will be an added advantage in enhancing the design process. Qualifications required for this role include: - BE in Electronics & Communication Engineering In addition to the above, Microchip Technology, Inc. offers a supportive work environment where you can be a part of a dedicated team that challenges the status quo and empowers innovation. With over 30 years of quarterly profitability, our company values employee development, values-based decision making, and a strong sense of community. Join us to be a part of a multi-billion dollar global organization that fosters career growth and stability. Please note that Microchip Technology Inc. does not accept unsolicited agency resumes and is not responsible for any fees related to unsolicited resumes.,

Role & responsibilities You will develop RTL code to implement FPGA-based digital designs , working from specification stage through to system integration . Projects will range from Mid to multi-million gates. Most projects include designing logic for latest generation of high speed serial protocols like PCIe gen5, Gen6, USB 3.2 Ethernet 10G/25G/100G , digital signal processing and control logic (bus interfaces and state machines) Understand the customer requirements and product definition Define architecture and detailed design spec based on requirements and various trade-offs Micro-architecture and coding of assigned module in VHDL/Verilog Write test bench for verifying design for complete scenario coverage Implementation of the design for porting on FPGA after required optimization based on available resources and timing closure requirement FPGA debugging and HW/SW integration Preferred candidate profile 9+ years of experience, including successful completion of FPGA based projects Coding experience in VHDL and/or Verilog is must Experience targeting Xilinx and/or Altera FPGAs required Familiarity with tools like Modelsim, Questasim, Xilinx Vivado, Planahead, Altera Quartus etc. is required Familiarity with debugging tools like Chipscope, Signal Tap, Logic analyzer, Scope, FPGA editor Implementation of designs with multiple clock domains is required Thorough understanding of appropriate coding styles for FPGAs , and trade-offs for density and speed Experience in RTL implementation of DSP algorithms will be appreciated Experience in development of PCIe, USB, Ethernet transceivers, DDRx, ADC, DAC, AMBA-AXI, SRAM, USB, UART, I2C, SPI will be appreciate Note - Position Open for FPGA based background profiles not for Hardware or Verification

At Cadence, we are seeking a talented individual to join our team and contribute to the world of technology. In this role, you will collaborate closely with various cross-functional teams across different locations to ensure alignment on project goals and deliverables. Your responsibilities will also include mentoring junior engineers, fostering innovation, and driving automation initiatives. The ideal candidate should hold a BE/B.Tech/M.E/M.Tech degree with at least 7 years of relevant work experience. A strong understanding of Design for Testability (DFT) concepts and excellent communication skills are essential. Additionally, hands-on experience with industry-standard EDA tools and logic simulators from various vendors is required. Proficiency in ATPG tools like Cadence Modus, RTL lint tools such as Jasper, and scan insertion is highly valued. Candidates with programming skills in Perl, Tcl, Python, or other scripting languages will be preferred. Experience in post-silicon validation, ATE debug, and support is desirable. Familiarity with RTL-to-GDS flow, synthesis, scan insertion, STA, and IR drop tasks is a plus. A good grasp of logic design, RTL implementation, verification, logic synthesis, Logic Equivalent Checking, and Static Timing Analysis is advantageous. As part of the team, you will play a crucial role in developing new DFT methodologies and solutions to enhance quality, reliability, and in-system test and debug capabilities. If you are passionate about making a difference in the technology industry and enjoy tackling complex challenges, we invite you to join us in our mission to solve problems that others cannot.,

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the worlds most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence's employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique One Cadence - One Team culture promotes collaboration within and across teams to ensure customer success. Multiple avenues of learning and development are available for employees to explore as per their specific requirements and interests. You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other every day. Location: Hyderabad BE/BTECH/ME/METCH or Equivalent Degree This is an opportunity to join a dynamic and growing team of experienced engineers developing high-performance physical IP for industry-standard protocols. The successful candidate will be a highly motivated self-starter who is able to work independently and collaboratively to complete tasks within required project timelines with high quality. The candidate will contribute to digital architecture, digital RTL, low power design, synthesis and timing analysis, and behavioral coding for all IPs in the SerDes physical IP portfolio as well as executing various tool flows for IP quality control. The candidate will be able to work as part of a small and focused team of engineers and will be able to collaborate successfully as needed with design architects, digital verification, project management, and digital and analog design teams in multiple worldwide geographies. This includes but is not limited to: - EXP-7-15years - Digital architecture that has an understanding of the trade-offs for power, performance, and area - Drive architecture to micro-architecture to RTL implementation with the refining of features/requirements throughout the design process - Understanding of synthesis, constraint generation, power management and DFT - Understanding of low-power designs and features (power islands, state retention, isolation) - Work with verification team to specify coverage points, testing strategy, corner conditions and stimulus creation - Familiarity with uC Based subsystems and their architecture Qualifications - 7+ Years experience in working with Digital Design and Architecture. - Must have good written and verbal cross-functional communication skills. - Proven experience in most of the following: - Design Architecture - Design implementation - Embedded uC Designs - Synthesis and SDC Creation - Scripting of design automation - Debugging verification test cases / SVAs to cover the design - Knowledge of existing Serial standards such as PCIE, USB, Ethernet, etc. - Must be comfortable interacting across the IPG development team including the ability to work with Mixed-signal, Verification and Analog teams - Knowledge of multiple programming languages. System Verilog, Python, C/C++, etc, are a plus - Working knowledge of revision control tools such as Perforce, Git, SVN is a plus - Education Level: Bachelor's Degree (MSEE Preferred),

As a Silicon Design Engineer at AMD, you will have the opportunity to work with formal experts and designers to verify formal properties and drive convergence. Your passion for modern, complex processor architecture, digital design, and verification will be put to good use in this role. You will be a key team player with excellent communication skills, strong analytical abilities, and problem-solving skills. Your willingness to learn and readiness to take on challenges will be crucial for success in this position. Your key responsibilities will include driving formal verification for the block, writing formal properties and assertions to verify the design, coordinating with RTL engineers to implement logic design for better clock gating, and verifying various aspects of the design. You will also be responsible for writing tests, sequences, and testbench components in SystemVerilog and UVM along with formal to achieve verification of the design. Additionally, you will be accountable for verification quality metrics such as pass rates, code coverage, and functional coverage. Preferred experience for this role includes project-level experience with design concepts and RTL implementation, familiarity with formal tools and/or functional verification tools by VCS, Cadence, Mentor Graphics, and a good understanding of computer organization/architecture. To qualify for this position, you should hold a Bachelor's or Master's degree in computer engineering or Electrical Engineering. Join AMD to be part of a culture that pushes the limits of innovation to solve the world's most important challenges. Together, we advance the building blocks for next-generation computing experiences in the data center, artificial intelligence, PCs, gaming, and embedded systems. At AMD, we strive for execution excellence while embodying qualities of being direct, humble, collaborative, and inclusive of diverse perspectives.,

As a Senior Director of Digital Design for New Product Development in Power Management at OnSemi in Bengaluru, India, you will be responsible for working on the development of power management products such as DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC drivers, Switches, and efuses for consumer, industrial, and automotive applications. Your role will involve collaborating with various product lines for RTL implementation of power converter controller design, digital design architecture, low power design, synthesis, timing analysis, and physical design interface for power management chips. You will work as part of a large team of engineers and collaborate with design architects, digital verification, project management, and digital/analog design teams globally. Your responsibilities will include implementing micro-architecture to RTL implementation, supporting the bring-up of features in pre-silicon platforms, owning the technical outcome of design, verification, and implementation of Power Management ICs, understanding project goals, leading and supporting customer issues, production issues, FW and system development, and supporting post-silicon validation activities. To qualify for this position, you should have a BS/MS in Electrical Engineering or a related field with 18/20 years of experience in Digital Design, Architecture, and ASIC/Mixed signal chip developments. The ideal candidate should have a thorough understanding of the end-to-end digital design flow, RTL design, CDC, ASIC synthesis, timing analysis, P&R, UPF, system Verilog, Verilog, TCL, and Perl/Python/XML programming languages. OnSemi, a company focused on automotive and industrial end-markets, is committed to driving disruptive innovations in megatrends such as vehicle electrification, safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a portfolio of intelligent power and sensing technologies, OnSemi aims to create a safer, cleaner, and smarter world. If you are a high-performance innovator looking to join a dynamic team in a forward-thinking company, OnSemi offers a positive recruitment experience and attractive company benefits. More details about the benefits can be found here: [OnSemi Career Benefits](https://www.onsemi.com/careers/career-benefits).,

As a Sr. Principal Digital Design Engineer at OnSemi in Bengaluru, India, you will be an integral part of the Power Management product development team, focusing on designing innovative solutions for consumer, industrial, and automotive applications. Your responsibilities will include collaborating with various product lines for RTL implementation of power converter controller designs, digital design architecture, low power design, synthesis, timing analysis, and physical design interface using state-of-the-art RTL2GDS flows. You will work closely with a dynamic team of engineers, design architects, digital verification, project management, and analog design teams across different geographies. Your role will involve implementing micro-architecture to RTL, supporting pre-silicon platforms, owning the technical outcome of Power Management ICs, and leading customer support, production issues, system development, and failure analysis. To excel in this role, you should possess a Bachelor's degree in Electrical Engineering with 12 years of experience or a Master's degree with 10 years of experience in Digital Design, Architecture, and ASIC/Mixed signal chip developments. A deep understanding of the digital design flow, RTL design, CDC, synthesis, timing analysis, system Verilog, Verilog, TCL, Perl/Python/XML programming languages, and various protocols is essential. Onsemi (Nasdaq: ON) is dedicated to driving disruptive innovations in automotive and industrial markets, aiming to accelerate change in megatrends such as vehicle electrification, sustainable energy grids, industrial automation, and 5G infrastructure. With a focus on intelligent power and sensing technologies, Onsemi is committed to creating a safer, cleaner, and smarter world. To learn more about our company benefits, visit: https://www.onsemi.com/careers/career-benefits Join us at Onsemi to be part of a high-performance team that fosters innovation and offers a positive recruitment experience, cultivating a strong brand as an exceptional workplace.,

You will be responsible for joining OnSemi's growing team in Bengaluru, India as a Sr. Principal Digital Design Engineer focused on New Product Development in Power Management. Your primary responsibilities will include working on the development of various Power Management products for consumer, industrial, and automotive applications such as DC-DC PMIC/POL, multiphase controllers, drivers, converters, LED drivers, SiC drivers, switches, and efuses. Your key responsibilities will involve collaborating with different product lines for RTL implementation of power convertor controller designs, working on digital design architecture, RTL, low power design, synthesis, and timing analysis. You will also interface with the Physical Design team for the power management chips using state-of-the-art RTL2GDS flows. As part of a large engineering team, you will collaborate effectively with design architects, digital verification, project management, and digital and analog design teams across various global locations. You will be involved in micro-architecture to RTL implementation, supporting system-level bring-up on pre-silicon platforms, and owning the technical outcome of Power Management ICs. Furthermore, you will be responsible for understanding project goals, executing with realistic schedules, reporting progress status, and supporting post-silicon validation activities. You will also lead and support customer issues, production issues, FW and system development, and failure analysis. Onsemi is a company driving disruptive innovations to create a better future, focusing on automotive and industrial end-markets. With a highly differentiated product portfolio, Onsemi aims to solve complex challenges and lead the way in creating a safer, cleaner, and smarter world. To qualify for this role, you should have a BS in Electrical Engineering or related field with 12 years of experience, or an MS with 10 years of experience in Digital Design, Architecture, and ASIC/Mixed signal chip developments. The ideal candidate will possess a thorough understanding of the end-to-end digital design flow, RTL design, CDC, ASIC synthesis, timing analysis, P&R, UPF, system Verilog, Verilog, TCL, and Perl/Python/XML programming languages.,

We are looking for talented RTL Designers to join our SoC Digital Design Team. This role involves contributing to the development of high-performance SoCs for the mobile space. The ideal candidate will have strong expertise in RTL-based digital design, excellent communication skills, and the ability to collaborate effectively with diverse global teams involved in the ASIC design lifecycle. You'll get the opportunity to work on cutting-edge SoCs that are shaping the future of mobile technology. Responsibilities: Develop micro-architecture and RTL implementation for System-on-Chips (SoCs). Take responsibility for block-level or full-chip integration and design . Be hands-on with Lint, CDC (Clock Domain Crossing), and LEC (Logic Equivalence Checking) tools, with a preference for experience in Low Power check tools . Possess a good understanding of design implementation flows and tools such as Synthesis, STA (Static Timing Analysis), and DFT (Design For Testability) . Have a good understanding and hands-on experience with database management flows , preferably ClearCase/ClearQuest . Collaborate with the functional verification team to review test plans and coverage . Experience with AXI/AHB protocols is essential. Knowledge of Networks on Chip Fabric and I/O protocols like SDCC/DDR/USB/UART/SPI would be a significant plus. Work seamlessly with global teams including ASIC design, IP, architecture, implementation, DFT, power, STA, PD, software, firmware, and validation teams. Required Skills and Qualifications: Excellent inter-personal and communication skills. Strong knowledge of digital design principles. Proficiency in RTL implementation. Familiarity with design verification processes.