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Cadence
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Principal Design Engineer

Principal Design Engineer

5 - 10 years

|

45 - 55 Lacs

Posted:10 hours ago| Platform:

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Skills Required

timing closure dft architecture debugging atpg presales silicon rtl ieee testing

Work Mode

Work from Office

Job Type

Full Time

Job Description

Experience: 5- 12 years

Location - Bangalore/Pune/Noida/Hyderabad

Responsibilities:

Complete DFT ownership of projects including:

Test architecture definition.
Identifying and implementing RTL changes for DFT.
Performing scan insertion, LEC checks, low power CLP checks.
Developing timing constraints for test mode timing closure.
Scan and ATPG for different fault models.
Boundary scan, ACJTAG, IEEE 1500 implementation and verification.
IEEE1687 (iJTAG) compliant ICL/PDL for functional manufacturing tests.
Running zero delay and timing simulations and debugging on all the above aspects.
Supporting post silicon bring up.
Interacting with customers on DFT aspects and support Marketing & Pre-Sales team.
Experience working on very high speed and low power designs.

.

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