Principal ASIC Digital Verification Engineer- IP Development

Synopsys

15 - 20 years

18 - 20 Lacs

bengaluru

Posted:1 day ago| Platform:

Apply

Skills Required

c++ iso usb semiconductor amba test cases rtl verification scripting axi vmm ahb perl protocols system verilog tcl programming functional safety asic python asic verification c ovm ip rtl fmeda uvm verilog ethernet ddr synopsys pcie

Work Mode

Work from Office

Job Type

Full Time

Job Description

Architecting and making strategic decisions on test bench design for IP Core verification.

Developing comprehensive verification plans and specifications based on functional requirements.
Implementing robust test bench infrastructure and authoring advanced test cases using UVM/VMM/OVM.
Driving a coverage-driven verification methodology to ensure thorough validation of IP functionality.
Leading technical aspects of the verification team, mentoring junior engineers and collaborating internationally.
Providing innovative verification solutions to enhance productivity, performance, and throughput.
Engaging in assertion-based verification and coverage closure to guarantee high-quality deliverables.
Collaborating with cross-functional teams on functional safety and compliance standards, such as ISO26262 and FMEDA.

The Impact You Will Have:

Enable Synopsys to deliver world-class, high-performance IP Cores to global customers in AI, automotive, and cloud sectors.
Enhance the robustness and reliability of verification processes, ensuring top-tier quality for end-customer applications.
Accelerate time-to-market for Synopsys IP products through optimized verification methodologies and best practices.
Drive collaboration and knowledge sharing across international teams, fostering a culture of innovation and excellence.
Support functional safety initiatives, contributing to the development of secure and compliant solutions for automotive and mission-critical domains.
Influence architectural decisions and technical strategies that shape the future of semiconductor verification.

What You ll Need:

Extensive hands-on experience (15+ years) in ASIC/RTL verification for complex IP Cores.
Deep knowledge of protocols such as DDR, PCIe, AMBA (AXI, CHI), SD/eMMC, Ethernet, USB, and MIPI.
Proficiency in verification methodologies: UVM, VMM, OVM; and SystemVerilog-based, object-oriented coding.
Strong skills in scripting/programming languages: C/C++, TCL, Perl, Python.
Experience in developing test environments, planning, coverage closure, and assertion-based verification.
Exposure to functional safety standards (ISO26262, FMEDA) is highly advantageous

More Jobs at Synopsys

Anaplan Model Builder - Senior Staff

Chennai, Pune, Delhi, Mumbai, Bengaluru, Hyderabad, Kolkata

3 - 8 yrs

INR 5 - 10 Lacs

Staff ASIC RTL Digital Design Engineer

Pune

5 - 10 yrs

INR 16 - 17 Lacs

Layout Design, Sr Engineer

Pune

2 - 3 yrs

INR 4 - 5 Lacs

ASIC DFT, Engineer

Hyderabad

Experience: Not specified

INR 18 - 20 Lacs

Sr. Staff ASIC Verification Engineer

Pune

8 - 9 yrs

INR 11 - 12 Lacs

Mock Interview

Practice Video Interview with JobPe AI

Start Python Interview

Start Your Job Search Today

Browse through a variety of job opportunities tailored to your skills and preferences. Filter by location, experience, salary, and more to find your perfect fit.