Posted:None|
Platform:
Work from Office
Full Time
General Summary:
Senior/Lead ASIC Verification Engineers with an experience of minimum 5+ yrsVery strong experience with Verilog, System Verilog and UVM
Working experience on development of Verification IP of layered protocol High Speed peripheral Interface protocol PCIe Gen4+ onwards, PCIe Experience is a must
Strong knowledge on UVM RAL and common register interfaces such as APB, AHB, AXI (ARM), RAM.
Working experience on scripting and automation
Strong Past experience of developing verification plan from scratch and testbench development using the detailed Specification and TestPlan from the scratchStrong base knowledge on digital design, blocks/components
Strong debugging skills and Good knowledge of assertions and functional coverage coding and closure.
Good knowledge on code coverage analysis and closure.
Good knowledge of any scripting language
Strong documentation and presentation skills.
Minimum Qualifications:
Qualcomm
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