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Posted:2 days ago| Platform: 
Work from Office
Full Time
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Strong expertise in Verilog, HVL(SV, Specman e) with UVM/OVM/eRM methodology Experience in assertions development/closure, constraint randomization, functional and code coverages, formal verification Experiences in test-bench development Strong RTL and GLS (w/ or w/o SDF) sim debug skills We re doing work that matters. Help us solve what others can t.
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Bengaluru
20.0 - 25.0 Lacs P.A.
Bengaluru
20.0 - 25.0 Lacs P.A.
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Hyderabad, Bengaluru
30.0 - 45.0 Lacs P.A.
