3 - 10 years
3 - 11 Lacs
Bengaluru / Bangalore, Karnataka, India
Posted:1 day ago|
Platform:
On-site
Full Time
Strong expertise in Verilog, HVL(SV, Specman e) with UVM/OVM/eRM methodology Experience in assertions development/closure, constraint randomization, functional and code coverages, formal verification Experiences in test-bench development Strong RTL and GLS (w/ or w/o SDF) sim debug skills
Cadence Design Systems
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