IP Design Verification Engineer

As the Turbo IP (TIP) Verification technical Lead, you will own and drive the verification strategy and execution for IP. This role requires deep technical expertise, leadership skills, and the ability to manage complex verification projects across global teams. You will collaborate with architecture, design, firmware, and validation teams to ensure first-pass success and high-quality deliverables.

Responsibilities

• Develop detailed test plans, coverage strategies, and verification metrics
• Drive adoption of best practices and continuous improvement in verification flows
• Lead and mentor a team of verification engineers, providing technical guidance and career development
• Oversee development of UVM-based testbenches, constrained-random stimulus, and coverage closure
• Manage regression infrastructure and ensure timely milestone completion
• Work closely with design, architecture, and post-silicon teams to resolve issues and optimize product quality
• Partner with cross-functional teams to ensure seamless integration and verification sign-off
• Champion adoption of formal verification, emulation, and automation techniques
• Explore AI/ML-driven solutions for coverage analysis, bug triage, and productivity improvements
• Ensure compliance with industry-standard verification practices and maintain high-quality standards
• Collaborate with architects, design, firmware, and validation teams to define verification requirements and close coverage
• Drive continuous improvement in verification methodologies, automation, and quality metrics
• Demonstrate innovation in verification processes, including AI/ML-driven verification or developing custom automation scripts
• Evaluate new verification technologies and incorporate them to continuously improve efficiency and effectiveness
• Foster a culture of innovation, accountability, and technical excellence within the team

• 15+ Years of total experience and minimum 10+ years of experience in ASIC/IP verification
• Deep expertise in IP and subsystem-level verification, including UVM/System Verilog, formal verification, and emulation
• Strong proficiency in System-Verilog, UVM, and advanced verification methodologies
• Hands-on experience with simulation tools such as VCS, Questa, or Xcelium and coverage-driven verification
• Deep understanding of high-performance IP architectures (Turbo IP or similar)
• Proven ability to lead and scale verification teams for complex projects Excellent problem-solving, debugging, and analytical skills
• Strong communication and stakeholder management capabilities
• Exposure to formal verification, emulation platforms, and FPGA prototyping
• Familiarity with scripting languages such as Python, Perl, or TCL for automation
• Experience leveraging AI/ML for verification productivity is a plus

Academic Qualifications: Bachelor's or Master's degree in Electrical/Electronics Engineering, Computer Engineering, or related field (Master's preferred)