8 - 13 years

9 - 13 Lacs

Posted:1 hour ago| Platform: Naukri logo

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Job Type

Full Time

Job Description

We are looking for an experienced

DFT Design Engineer

with strong hands-on expertise in Design-for-Testability methodologies. The ideal candidate should have in-depth knowledge of DFT architectures, scan methodologies, and proven experience using Synopsys DFT tools.

Key Responsibilities

  • Develop and implement DFT architectures including

    JTAG

    ,

    Scan

    ,

    Scan Compression

    , and

    Boundary Scan

    .
  • Define and integrate DFT structures during RTL and gate-level design phases.
  • Perform scan insertion, ATPG, and pattern generation using

    Synopsys DFT tools

    .
  • Work closely with design, verification, and physical design teams to ensure test coverage and quality.
  • Debug DFT-related issues during synthesis and post-silicon validation.
  • Ensure compliance with DFT standards and best practices.

Required Skills & Qualifications

  • 8+ years of experience in

    DFT Design

    for complex SoCs.
  • Strong understanding of

    DFT architectures

    such as JTAG, Scan, Scan Compression, and Boundary Scan.
  • Hands-on experience with

    Synopsys tools

    (eg, DFT Compiler, TetraMAX).
  • Solid knowledge of digital design fundamentals and test methodologies.
  • Experience in improving fault coverage and test efficiency.

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