777 Fpga Jobs - Page 19

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 1-3 years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

As a Logic design lead in the IBM Systems division, you will be responsible for the micro architecture, design and development of a high-bandwidth, low-latency on-chip interconnect (NoC) and chip-to-chip interconnect and integration into high-performance IBM Systems. Design and architect different interconnect topologies as driven by bandwidth, latency and RAS requirements Develop the features, present the proposed architecture in the High level design discussion Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW teams to develop the feature Signoff the Pre-silicon Design that meets all the functional, area and timing goals Participate in silicon bring-up and validation of the hardware Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8+ years of relevant experience - At least 1 generation of processor interconnect design delivery leadership (eg UPI, axi, amba, NoC). - Expertise of SMP coherency - Experience in different on-chip interconnect topologies (e.g., mesh, crossbar) - Understanding of various snoop and data network protocols - Understanding of latency & bandwidth requirements and effective means of implementation - Working knowledge of queuing theory - numa/nuca architecture - Proficient in HDLs- VHDL / Verilog - Experience in High speed and Power efficient logic design -Experience in working with verification, validation, physical design teams for design closure including test plan reviews and verification coverage - Good understanding of Physical Design and able to collaborate with physical design team for floor planning, wire layer usage and budgets, placement of blocks for achieving high-performance design - Experience in leading uarch, RTL design teams for feature enhancements.

-Lead the Architecture, Design and development of processor L2 and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -4+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

Location: Bangalore, India Thales people architect solutions that enable two-thirds of planes to take off and land safely. We create in-flight entertainment systems that engross 50 million fliers every year and we develop the avionics that control the world s largest commercial aircrafts. Our simulators train the next generation of pilots for fighter jets, transporters and search and rescue helicopters. And, together, each and every member of our aerospace team makes a difference. Hardware Architect for Electronic design Thales India Engineering Competency Center (ECC) in Bangalore is seeking a Technical Lead/Sr Technical lead to be part of Hardware engineering team. In this role, you will be responsible for Hardware subsystems architectural design, trade-off analysis, feasibility studies, Proposal preparation, Project scheduling/costing, Project monitoring and managing and IVVQ for various Thales products (Defense and aerospace applications). You will be coordinating with the Solution/System Architect and the Project Design Authority (PDA) to ensure consistency with the Solution/System architecture and with the hardware, industry and procurement strategies. Necessary to technically and functionally co-ordinate with engineers of hardware disciplines such as Board design (digital, analog, RF and power supplies), FPGA design (FPGA, ASIC), low-level software (in agreement with the software architect), mechanical design, testability and means of tests, industrial design (in agreement with the Head of Industry). This position requires having good level of expertise in its hardware product design, development and qualification. Qualifications: B.Tech/B.E in Electronics, Instrumentation engineering or equivalent with 10 to 16 years of relevant experience. Higher qualifications of Masters or Post-graduation is desirable. Domain experience in Avionics systems or defense system is desirable. Responsibilities: Develop, stabilize and maintain hardware architecture for all phases of the life cycle from design to delivery to customer. Perform trade-off analysis of different technologies and feasibility studies to propose the best architecture design Implement architecture choices based on trade-offs between cost, supply chain, customer requirements and technology possibilities Lead and coordinate the architectural studies of Hardware under his responsibility Perform trade-off analysis of different technologies and feasibility studies to propose the best architecture design Identify risks and opportunities related to the hardware architecture Propose and implement risk reduction plans and opportunities for validation Preparing project proposal including schedule and efforts Preparation of the associated project documentation and reviews Coordinating with different stakeholders like Industrialization, IPO, suppliers, engineering, WPM, customer to prepare the optimal project proposals Integration of Hardware, Software and Firmware and performs IVVQ Collaborative work applying quality standards and internal processes Ensure compliance with standards, product development plans (reuse policy), material, industrial and purchasing strategies Skills experience: Must have strong experience in complete Hardware certified development life cycle (Technical feasibility, requirements writing, preliminary and detailed design, prototype manufacturing, test and evaluation, qualification and certification) Must have gained experience in piloting a lot of development work, involving in product testing in external labs for hardware products Must have experience in the IVVQ (Integration, Verification, Validation and Qualification) including requirements management Must have strong experience of integration of Hardware, FPGA firmware, mechanical packaging, low-level software and application software on Hardware unit. Must have good experience in bench test set-up, functional testing and performance evaluation Must have experience in developing IVV Test procedures (PVP/ATP), Test Reports (PVR/ATR), Qualification by similarity reports (QBSR) and other documents required by certification authorities for airborne products. Must have strong experience to troubleshoot on electronics and embedded hardware systems to find the root cause and to fix with a suitable solution. Must have experience to ensure the reporting progress of the project along with KPI. Must have experience to manage risks and opportunities at Hardware solution architecture. Must be rigorous, organized, autonomous and proactive, and motivated by a position within a multidisciplinary team. Must have demonstrated leadership skills on complex topics. Must have experience of working with multi-disciplinary team (BL engineering team, Lab technicians, external labs, Purchase team, Engineering teams and manufacturing teams) Must have experience in interfacing with external test facilities for environmental and EMI/EMC and other electrical tests as per MIL-STD/IEC61000/DO-160 standards. Should be familiar with Knowledge of production trades: procurement, manufacturing, delivery Knowledge of Certification DO254/DO160, Safety of aeronautical systems (ARP4761), and Knowledge of ARP4754B will be helpful. Product knowledge in avionics fields: civil and military calculators, displays, inertia, GNSS, probes will be helpful. Excellent communication and collaboration skills in an international multi-cultural environment (France, Canada, India, UK). Ability to work across different departments and establish effective relationships.

Analog Devices is seeking an experienced and strategic Director of Embedded Software Development Engineering to lead a multi-disciplinary embedded software development team. This role plays a critical part in enabling the next generation of Linux and Zephyr based embedded platforms within ADI s growing SoC portfolio. As a senior technical leader, you will oversee all aspects of software development for platform enablement, including secure ROM bootloaders, board support packages (BSPs), low-level drivers, and SDK infrastructure. You will build and grow a high-performing team in Bangalore while collaborating closely with global peer groups and stakeholders in silicon, SW HW architecture, applications, and tools teams. Key Responsibilities Bangalore Team Leadership: Lead and grow a multidisciplinary software engineering team focused on SDK, ROM, and BSP development. Act as the senior technical and people leader at the Bangalore site for this domain. Platform Enablement: Development and maintenance of ROM code, secure boot frameworks, device initialization, and board support packages (BSPs) for ADI s Linux-capable SoCs. SDK Development: Contribute key components of ADI s SDK ecosystem, ensuring scalable, reusable, and maintainable solutions that simplify embedded software development for customers. Cross-Functional Alignment: Collaborate with global SDK team, SoC SW architecture, embedded Linux, Zephyr, security, and tools teams to align software deliverables with silicon features and go-to-market strategies. Software Quality Processes: Establish and maintain best-in-class software engineering practices including code review, CI/CD pipelines, test automation, and security hardening. Talent Culture Development: Hire, mentor, and develop top engineering talent in Bangalore, creating a culture of technical excellence, ownership, and continuous improvement. Pre-silicon bring-up: Closely collaborate with HW and design verification teams to develop and execute pre-silicon SW development strategy to ensure software readiness for internal and customer-facing deliverables. Support pre-silicon and post-silicon bring-up. Required Qualifications Bachelor s or Master s degree in Computer Science, Electrical Engineering, or related discipline 15+ years of embedded software experience, with 5+ years in senior engineering leadership roles Deep technical expertise in embedded Linux, ROM bootloaders, and BSP development Experience in pre-silicon software development strategies (virtual platforms, emulation platforms, FPGA emulation) Proven experience with ARM-based SoC architectures and secure boot flows Strong leadership in distributed and cross-functional environments with open and inner-source mindset Proficiency with modern development tools: Git, Jenkins, Yocto, U-Boot, Linux kernel, etc. Excellent verbal and written communication skills with global collaboration experience Preferred Qualifications Experience in semiconductor or OEM companies delivering SoC platform software Familiarity with software safety and security standards (e.g., IEC 61508, ISO 21434) Experience with automotive and/or industrial embedded systems Background in open-source contributions or community engagement Prior experience building and scaling engineering teams in India

Grow with us About this opportunity We are seeking a Tech Lead FPGA/ASIC Verification to join the Ericsson Silicon organization. In this key role, you will provide strategic leadership to a team of dedicated engineers focused on developing world-class Radio and RAN Compute products. You will lead the FPGA verification team in defining, implementing, and optimizing verification strategies and environments for high-efficiency data transfer and processing with embedded subsystems. As part of our global organization, youll collaborate with talented teams across our various sites. We are committed to Agile principles, fostering a collaborative and innovative work environment that encourages creativity, teamwork, and strategic thinking What you will do Lead the definition of advanced verification requirements and strategies for FPGA and/or ASIC designs based on functional specifications and Ericsson development processes. Architect and implement comprehensive verification environments and test cases to execute verification plans, ensuring high quality deliverables. Analyze and optimize functional and code coverage metrics, driving towards completion targets and continuous improvement. Debug RTL in collaboration with designers, Collaborate with hardware, software, systems, and integration teams to understand overall product requirements and drive strategic and efficient solutions. Champion the continuous improvement of products, tools, and processes, contributing thought leadership and innovative ideas. Produce and oversee the generation of comprehensive verification documentation, ensuring clarity and precision including test procedures and results documentation. Devise test plans that cover functional verification and on target lab verification. Provide mentoring and guidance to team member. You will bring 10+ years of experience in FPGA/ASIC verification, including leadership roles. Exceptional knowledge of UVM and SystemVerilog Proven ability to architect and create RTL testbenches from scratch, demonstrating advanced technical skills. Strong knowledge of object-oriented programming and embedded software design and testing. Expertise with modern FPGA device families and tools Experience with scripting languages such as Python, Tcl, shell scripting, etc. An analytical and strategic approach with a results-oriented mindset and the ability to deliver under pressure. Excellent English verbal and written communication skills, with the ability to convey complex ideas clearly and persuasively. High self-motivation and the ability to work independently while leading and inspiring teams. A track record of successful cross-team and cross-site cooperation, including leadership roles. A Bachelors degree in Electrical or Computer Engineering or equivalent. Why join Ericsson What happens once you apply Primary country and city: India (IN) || Bangalore Req ID: 768586

Grow with us About this opportunity We are seeking a Tech Lead FPGA/ASIC Verification to join the Ericsson Silicon organization. In this key role, you will provide strategic leadership to a team of dedicated engineers focused on developing world-class Radio and RAN Compute products. You will lead the FPGA verification team in defining, implementing, and optimizing verification strategies and environments for high-efficiency data transfer and processing with embedded subsystems. As part of our global organization, youll collaborate with talented teams across our various sites. We are committed to Agile principles, fostering a collaborative and innovative work environment that encourages creativity, teamwork, and strategic thinking What you will do Lead the definition of advanced verification requirements and strategies for FPGA and/or ASIC designs based on functional specifications and Ericsson development processes. Architect and implement comprehensive verification environments and test cases to execute verification plans, ensuring high quality deliverables. Analyze and optimize functional and code coverage metrics, driving towards completion targets and continuous improvement. Debug RTL in collaboration with designers, Collaborate with hardware, software, systems, and integration teams to understand overall product requirements and drive strategic and efficient solutions. Champion the continuous improvement of products, tools, and processes, contributing thought leadership and innovative ideas. Produce and oversee the generation of comprehensive verification documentation, ensuring clarity and precision including test procedures and results documentation. Devise test plans that cover functional verification and on target lab verification. Provide mentoring and guidance to team member. You will bring 10+ years of experience in FPGA/ASIC verification, including leadership roles. Exceptional knowledge of UVM and SystemVerilog Proven ability to architect and create RTL testbenches from scratch, demonstrating advanced technical skills. Strong knowledge of object-oriented programming and embedded software design and testing. Expertise with modern FPGA device families and tools Experience with scripting languages such as Python, Tcl, shell scripting, etc. An analytical and strategic approach with a results-oriented mindset and the ability to deliver under pressure. Excellent English verbal and written communication skills, with the ability to convey complex ideas clearly and persuasively. High self-motivation and the ability to work independently while leading and inspiring teams. A track record of successful cross-team and cross-site cooperation, including leadership roles. A Bachelors degree in Electrical or Computer Engineering or equivalent. Why join Ericsson What happens once you apply Primary country and city: India (IN) || Bangalore Req ID: 768584

Job Description Danfoss Drives is looking for an Senior Engineer Power Electronics to join our diverse team at their Oragadam/Chennai Campus, India . Job Responsibilities Responsibilities for this position include, but are not limited to, the following. Design, selection, specification, Analyses failures seen on the product and find root cause and implement improvements. Participate in idea generation on cost down possibilities. Support Testing Personals during the Product testing Familiarity with Product Life cycle change management process and documentation Provide technical clarification of designs with suppliers and manufacturing Prepare Technical documentation according to required standards Assist in solving critical customer cases and provide technical inputs to customer queries. Work with a multi-disciplinary engineering development team that includes application engineering, controls engineering control hardware design, and test / validation. Work with supply chain teams and qualify components and assemblies during implementations and resolve issues as needed to maintain product and project quality, cost and deliverables Background Skills The ideal candidate possesses these skills. B.E (EEE/ECE/Power Electronics) or ME /M.Tech on Power Electronics and Drives Experience of 5 to 7 years on Working knowledge on power electronics devices (MOSFETs, IGBTs, SCRs) and circuits like converter, inverter , SMPS. Experience and working knowledge on passive components like Capacitors, Inductors, and resistors. Experience with analog electronics such as operational amplifiers, Comparators, multipliers, signal conditioning, filters etc. Knowledge on digital electronics including DSP, Microcontrollers FPGA s and its design implementations Familiarity with Instrumentation and measurement of power converters Demonstrated ability to meet goals and objectives. Effective technical documentation skills Familiarity with IEC, UL, and CSA regulatory standards. Experience in Analog and Digital circuit design and development. EMI/EMC design, EMI/EMC test/debug, reliability test and system integration Knowledge in using Cadence for PCB Board layout , PCB fabrication, assembly, and testing. Danfoss Engineering Tomorrow At Danfoss, we are engineering solutions that allow the world to use resources in smarter ways - driving the sustainable transformation of tomorrow. No transformation has ever been started without a group of passionate, dedicated and empowered people. We believe that innovation and great results are driven by the right mix of people with diverse backgrounds, personalities, skills, and perspectives, reflecting the world in which we do business. To make sure the mix of people works, we strive to create an inclusive work environment where people of all backgrounds are treated equally, respected, and valued for who they are. It is a strong priority within Danfoss to improve the health, working environment and safety of our employees.

As a Wired System Architect, you will be responsible for participating in standards bodies and understanding wired comms technology trends, defining products (silicon, IP, boards), defining system reference designs & implementation, system architecture engagement with customers, ecosystem partner engagements for solution development, and sales & field enablement for AMD technology adoption. This role requires prior experience in system architecture, systems engineering, design & implementation, test & validation, performance benchmarking preferably at leading OEMs for comms infrastructure segments such as packet/ optical networks, security data & control path, datacenter interconnect, enterprise/ service provider broadband access, and emerging AI ML model inference applications in wired networks. THE PERSON : The ideal person has outstanding problem-solving skills, analytical skills, attention to design details, creative & out of box thinking, interpersonal skills at driving collaboration across cross-functional teams for common goals, penchant for listening to/ learning from peers, persistence & perseverance at the face of obstacles, patience to iterate for optimal solution, and ability to document & share best design practices. AMD culture of execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives is critical for success in this role. KEY RESPONSIBILITIES: Specify product roadmaps for FPGA/SoC, IP, custom ASIC aligned with technological trends and emerging use cases Identify customer system requirements, develop system architecture proposals to help customer differentiate, lower cost, power, and TTM Contributing to business strategy & successful execution of strategy to fruition, sales and field training/ enablement and demand generation Identify Define system design requirements, design & implementation of system reference designs Guide/ mobilize/ and work with internal engineering teams and partner ecosystem for timely execution of IP and system reference designs Collaborate with Silicon and Tools marketing teams for alignment and execution on product/ market requirements Enable sales and field to drive AMD technology adoption for successful execution on business, revenue, and profitability goals PREFERRED EXPERIENCE: 15+ years of experience in design and development of wired subsystems at leading OEM vendors using FPGA/ SoC and/ or ASICs Deep knowledge of Ethernet protocols and associated security standards, packet/ optical networks, and broadband access technologies Expert levels skills in RTL design, FPGA tools and/or ASIC design methodologies Experience in wired subsystem design performance benchmarking, power optimization, and system thermal design considerations Ability to operate effectively in a fast-paced environment with changing deadlines Strong project management, process management, analytical and consulting skills

Senior Software Engineer The Software Engineering team delivers next-generation application enhancements and new products for a changing world. Working at the cutting edge, we design and develop software for platforms, peripherals, applications and diagnostics all with the most advanced technologies, tools, software engineering methodologies and the collaboration of internal and external partners. Join us to do the best work of your career and make a profound social impact as a Senior Software Engineer on our Software Engineering Team in Bangalore. What you ll achieve As a Senior Software Engineer, you will be responsible for developing sophisticated systems and software basis the customer s business goals, needs and general business environment creating software solutions. You will: A BE/ME degree in ECE, CE, CS with 5-8 years of industry experience in System Management software development, strong firmware / System development background with strong C/C++ development/debug skills and Strong in Embedded Linux programming, OS Internals, memory management, IPC, thread programming and embedded application software development. Strong experience in IPMI, DMTF, RedFish, CIM, CIMOM, Linux. Solid understanding of SNMP, IPMI protocols. Experience/exposure to I2C, MCTP, NCSI, PLDM, uEFI protocol is a plus. Working experience with peripheral hardware devices like PCIe Switch, NIC, GPU, FPGA, Memory controller etc. is a plus. Good Knowledge on Storage domain Take the first step towards your dream career Every Dell Technologies team member brings something unique to the table. Here s what we are looking for with this role: Essential Requirements Validated knowledge of programming languages; operating systems; firmware; BIOS; device drivers; databases; system, network, operating system, and application administration; embedded software/firmware; tools and utilities Ability to code/debug more sophisticated programs using either written or verbal design specifications Capacity to achieve proficiency of new tools, languages and operating systems with training and on-the-job experience 5-8 years of related experience Desirable Requirements Bachelor s degree Application closing date: 30 June 2025 #NJP

Grow with us About this opportunity We are seeking a Tech Lead FPGA/ASIC Verification to join the Ericsson Silicon organization. In this key role, you will provide strategic leadership to a team of dedicated engineers focused on developing world-class Radio and RAN Compute products. You will lead the FPGA verification team in defining, implementing, and optimizing verification strategies and environments for high-efficiency data transfer and processing with embedded subsystems. As part of our global organization, youll collaborate with talented teams across our various sites. We are committed to Agile principles, fostering a collaborative and innovative work environment that encourages creativity, teamwork, and strategic thinking What you will do Lead the definition of advanced verification requirements and strategies for FPGA and/or ASIC designs based on functional specifications and Ericsson development processes. Architect and implement comprehensive verification environments and test cases to execute verification plans, ensuring high quality deliverables. Analyze and optimize functional and code coverage metrics, driving towards completion targets and continuous improvement. Debug RTL in collaboration with designers, Collaborate with hardware, software, systems, and integration teams to understand overall product requirements and drive strategic and efficient solutions. Champion the continuous improvement of products, tools, and processes, contributing thought leadership and innovative ideas. Produce and oversee the generation of comprehensive verification documentation, ensuring clarity and precision including test procedures and results documentation. Devise test plans that cover functional verification and on target lab verification. Provide mentoring and guidance to team member. You will bring 10+ years of experience in FPGA/ASIC verification, including leadership roles. Exceptional knowledge of UVM and SystemVerilog Proven ability to architect and create RTL testbenches from scratch, demonstrating advanced technical skills. Strong knowledge of object-oriented programming and embedded software design and testing. Expertise with modern FPGA device families and tools Experience with scripting languages such as Python, Tcl, shell scripting, etc. An analytical and strategic approach with a results-oriented mindset and the ability to deliver under pressure. Excellent English verbal and written communication skills, with the ability to convey complex ideas clearly and persuasively. High self-motivation and the ability to work independently while leading and inspiring teams. A track record of successful cross-team and cross-site cooperation, including leadership roles. A Bachelors degree in Electrical or Computer Engineering or equivalent. Primary country and city: India (IN) || Bangalore Req ID: 768584

Job Details: : Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design and integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design. Participates in the definition of architecture and microarchitecture features of the block being designed. Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Follows secure development practices to address the security threat model and security objects within the design. Works with IP providers to integrate and validate IPs at the SoC level. Drives quality assurance compliance for smooth IPSoC handoff. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: A bachelors degree in electrical/computer engineering, Computer Science or related field with 6+ years of experience (or) a masters degree with 4+ years of experience. Preferred Qualification: Relevant experience with skills in SoC flows, RTL integration and Globals (Clocking, Boot/Reset/Fabrics, DfD, Fuse, etc). Experience in subsystem design and HSIO protocols such as PCIe, UCIe is a plus. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Job Details: : Performs functional verification of IP logic to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Participates in the definition of verification infrastructure and related TFMs needed for functional design verification. Qualifications: Candidates must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. listed below would be obtained through a combination of Industry job-relevant experience, internship experiences and or schoolwork/classes/research. Education Requirement- Bachelors degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 6-8 years of industry work experience, or- Masters degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 5-7 years of industry work experience, or- PhD in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 4 years of related work experience. Minimum Qualifications- 4+ years of experience in relevant Pre-Silicon validation position having gone through multiple project cycles to gather in-depth experience. 4+ years of experience in logic design verification with various tools and methodologies including System Verilog, Perl, OVM/UVM, logic simulators, and coverage tools. 4+ years of experience with pre-silicon simulation tool flows such as Synopsys VCS Verdi and DVE. 4+ years of experience in OVM/UVM for developing verification test benches and constrained random verification. Preferred Qualifications- Experience with PCIe, Power Management, Ethernet, Network packet processing. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Job Details: : We are seeking a passionate and experienced Embedded Firmware and Driver Engineer to design, develop, and optimize low-level embedded software for Intels AI accelerators and GPUs. In this role, you will collaborate with a cross-geo team to create world-class embedded software solutions. Your responsibilities will includeDesigning, developing, and maintaining bare-metal firmware for ARC-based processors. Creating and managing Boot ROM and Boot loader systems. Developing and maintaining RTOS-based device drivers. Delivering new features requested by Cloud Service Providers. Solving complex technical problems and contributing to innovative solutions. Collaborate with hardware, system, and driver teams for feature definition and end-to-end delivery Qualifications: Minimum qualifications: Bachelors degree in computer science, Electrical Engineering, or a related field with at least 8 years of relevant experience in Embedded Software Design and Development. Proficiency in ARC or other low-power controller architectures. Expertise in C programming and basic understanding of assembly language. Deep understanding of real-time systems, interrupt handling, and RTOS (e.g. Zephyr) Proven experience in writing boot firmware Familiarity with communication protocols such as SPI, I2C, and UART. Excellent analytical and problem-solving skills, with the ability to manage stakeholders and collaborate across geographies. Exceptional written and oral communication skills. Hands-on experience in developing and integrating RTOS based device drivers. Preferred qualifications: Knowledge of interfaces like I3C, PCIe, CXL, and protocols such as SMBUS/PMBUS and MCTP/PLDM. Experience in pre-silicon emulation, simulation, and FPGA platforms, along with debugging tools like Lauterbach and protocol analyzers. Knowledge in one or more of the following areasConfidential Computing, UCIe, or HBM technologies. Understanding of DVFS algorithms, AVS, and thermal management strategies Familiarity with secure boot, firmware update mechanisms, and memory management and open-source projects like buildroot-external. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intels transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. *

Job Details: : Builds emulation and FPGA models and solutions from RTL design using synthesis, partitioning, and routing tools. Develops, integrates, tests, and debugs hardware and software collateral in simulation, emulation, and FPGA models for testing new features, writes directed tests, develops the test environment and hybrid emulation environment, and supports verification of hardware and software/firmware. Defines and develops new capabilities and tools to achieve better verification through improved emulation and FPGA model usability. Enables acceleration of RTL development and improve emulation/FPGA model usability for presilicon verification, postsilicon validation, and software development. Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform and interfaces with and provides guidance to verification teams for optimizing presilicon verification environments, test suites, and methodologies for emulation efficiency. Develops and utilizes automation aids, flows, and scripts in support of emulation utilization. Applies understanding of emulation and FPGA prototyping tools and methodologies, SoC integration, emulation transactors, emulation performance and optimization techniques, RTL simulation, and hybrid emulation environments (virtual platform and FPGA/emulation model). Collaborates with design, power and performance, silicon validation, and software teams, and participates in SoC and IP bring up, root causes testbench issues, IP and SoC testcases, and emulator/FPGA environment issues. Qualifications: Bachelor Degree in Electrical and Electronics Engineering or Masters Degree in Electrical and Electronics Engineering or Computer Engineering with 8+ years experience. Experience in Pre-si/post-Si validation with FPGA based validation, Experience with bring up of functional tests on FPGA/Si. Experience in Hardware validation/emulation platforms like zebu, veloce or functional bring up of PM/Reset/PCIE/DMI/DDR/Mem et.al. Good understanding of SoC architecture / uArchitecture, Networking protocols or Signal processing algorithms/flows in hardware. Excellent understanding of test framework and abstraction, develop test plans, test scripts for functional validation. Very good debugging skills, experience of working with various hardware debugging tools JTAG, Verdi, fsdb analysis. Good knowledge in C/C++, Scripting knowledge (Python/Perl/Tcl), ability to develop parsers. Knowledge in RTL design, VHDL/Verilog is a plus. Strong analytical ability, problem solving and communication skills. Ability to work independently and at various levels of abstraction. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. *

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI the next era of computing. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life s work, to amplify human imagination and intelligence. Make the choice to join us today. NVIDIA is an equal opportunity employer. We are now looking for a DFT Verification Engineer. Design-for-Test (DFT) Engineering at NVIDIA works on groundbreaking innovations every day involving crafting creative solutions for DFT architecture, implementation, verification and post-silicon validation on some of the industrys most complex semiconductor chips. We use the best industry tools and go beyond with internal methodologies to address some of NVIDIAs unique challenges. We are looking for you to implement the best verification methodologies for DFT IP at unit and system levels. You will bring in expertise in SystemVerilog, UVM, FPGA and Emulation application in DFT domain. What youll be doing: As a member of our team, You will build "state of the art" verification test benches and methodologies to verify DFT features in complex IPs/Sub-systems/SOCs. Develop and own verification environment using UVM or equivalent. Your responsibility will include to build reusable bus functional models, monitors, checkers and scoreboards. Own functional coverage driven verification closure and own design verification sign-offs at multiple levels. Collaborate closely with multi-functional teams like chip architecture, ASIC design, functional verification, and post silicon teams. Will be part of innovation to strive to improve the quality of DFT methods What we need to see: BSEE with 3+ or MSEE with 2+ years of experience in IP verification or related domains Expertise in System Verilog and verification methodologies like UVM/VMM. Expertise in prototyping, verification and debug tools (Emulation, FPGA, VCS, Debussy, Formality, PrimeTime etc). Good exposure to ASIC design methodologies: RTL design, clocking, timing and low-power architectures. Strong programming/scripting skills in C++, Perl, Python or Tcl Excellent written and oral communication skills Excitement to work on rare challenges Strong analytical and problem solving skills Ways to stand out from the crowd: Strong experience or interest in both DFT and RTL Verification domains Knowledge in Formal verification methodologies and tools for IP and SoC level verification Hands-on experience in post silicon debug on ATE and/or system labs. #LI-Hybrid

Role & Responsibilities: Collaborate with cross-functional teams including hardware engineers, software developers, and medical experts to design, develop, and test embedded software and FPGA solutions. Develop firmware for FPGAs from vendors such as Xilinx Zynq, Lattice Semiconductor, and Texas Instruments , including SoC implementations and hardware/software co-design . Optimize and implement image and video processing algorithms on embedded platforms and FPGA architectures. Integrate and support FPGA/ASIC-based ISP blocks , ensuring high performance and accuracy in medical imaging applications. Work with SoCs with integrated ISP (e.g., Qualcomm, NVIDIA Jetson, Ambarella, MediaTek) and manage interaction with hardware accelerators. Design and develop firmware for STM32 microcontrollers , with a focus on motion control , real-time responsiveness , and precision actuation . Develop and implement motion control algorithms, including PID control and motor driver integration, for high-precision diagnostic instruments. Implement and optimize communication protocols such as SPI and UART to support system communication and control flows. Utilize real-time operating systems (RTOS) or bare-metal firmware development for deterministic system behavior. Perform thorough testing, debugging, and optimization using tools like oscilloscopes , logic analyzers , and JTAG debuggers . Support product design lifecycle activities including requirements specification , firmware documentation , and design reviews . Preferred candidate profile: Education: Bachelors or Masters degree in Electrical Engineering, Computer Science, or related field. A Ph.D . is a plus for R&D or algorithm-intensive roles, particularly in imaging or signal processing. Professional Experience: 3+ years of hands-on experience in embedded firmware development with strong C/C++ proficiency. Proven experience with FPGA design using VHDL/Verilog , and development with tools like Vivado, Quartus, or Diamond. Experience working with STM32 microcontrollers , including development environments like STM32CubeIDE and IAR Embedded Workbench. Core Technical Expertise: Deep understanding of: SoC and camera architectures Memory hierarchy, DMA engines, cache control, and hardware accelerators Motion control techniques for motor and actuator systems Image Signal Processing (ISP) pipelines: demosaicing, AWB, AE, gamma, sharpening, etc. Familiarity with Linux kernel camera subsystems (e.g., V4L2) . Ability to optimize embedded code for performance, power, and latency. Desirable Knowledge Knowledge of medical device standards and regulations such as ISO 13485 and IEC 62304 . Familiarity with image quality tuning tools (e.g., Imatest, DxO Analyzer). Experience with real-time data acquisition, frame synchronization , and multithreaded image capture pipelines . Soft Skills Strong problem-solving and debugging skills in complex embedded systems. Excellent communication and collaboration abilities, with experience working in interdisciplinary teams .

Job Description This is an urgent requirementimmediate availability is highly desirable Job Title: Software Defined Radio (SDR) Developer Industry: Electronics / Telecommunications Location: Hyderabad, India Qualification: B.Tech / M.Tech (preferred) Experience: 310 years (flexible based on skills) Job Description: We are looking for a Software Defined Radio (SDR) Developer with strong expertise in wireless communication and digital signal processing. The ideal candidate will have hands-on experience in SDR implementation on FPGA/SoC platforms and be passionate about working on cutting-edge communication technologies. Key Responsibilities: Implement and optimize channel encoding/decoding techniques in digital communication systems. Design and simulate digital modulation schemes including BPSK, QPSK, 8PSK, and QAM. Develop and test digital filters (FIR/IIR) for communication applications. Work with Zynq Ultrascale and Kria SoM platforms; port applications to PetaLinux . Program and integrate systems using FPGA, DSP, and ARM processors . Contribute to the physical layer (PHY) development of wireless systems and modems. Understand and implement Software Communications Architecture (SCA) standards . Collaborate with hardware and software teams to deliver robust SDR solutions. Desired Skills: Strong knowledge of wireless communication protocols and PHY layer development Expertise in Verilog / VHDL for FPGA development Experience with SoC/SoM platforms and embedded Linux environments Hands-on skills in modem development , signal processing, and algorithm implementation Familiarity with communication system simulators like MATLAB/Simulink is a plus Application Details: If this opportunity aligns with your experience and interests, please send your updated resume along with the following details to chinmaya@topgearconsultants.com Current Location: Preferred Location: Highest Qualification: Total Experience: Current CTC: Expected CTC: Notice Period: Availability for Interview (Date & Time): We look forward to connecting with candidates passionate about building the next generation of wireless technologies.

Job Overview : We are looking for an experienced C++ Developer with deep expertise in SNORT rule sets, compiler development, and FPGA-accelerated processing. This role requires a strong foundation in system-level programming, along with the ability to work on performance-critical data path processing for network security applications. Key Responsibilities : - Design and develop a C++/C-based compiler to convert SNORT rule sets into state tables - Implement regex lookup engines integrated with FPGA-based acceleration - Optimize rule parsing, conversion logic, and data path evaluation pipelines - Collaborate with hardware (FPGA) teams to align on rule engine performance - Handle result processing logic for high-speed data inspection - Ensure software meets security, latency, and throughput requirements - Communicate directly with the client for requirement gathering and technical clarifications Requirements : - 8 - 12 years of experience in C++/C development, with strong system-level programming skills - Hands-on experience with SNORT rule sets, IDS/IPS systems, or similar network security tools - Experience in compiler or parser development, preferably with experience in state machine generation - Good understanding of regular expressions, pattern matching, and performance optimization - Exposure to FPGA-accelerated architectures and hardware-software interfacing is a plus - Excellent analytical, debugging, and communication skills - Ability to interact effectively with clients and cross-functional teams Preferred Skills : - Familiarity with network protocols and deep packet inspection - Experience with rule optimization, rule merging, and traffic flow classification - Prior experience in cyber security product development or telecom network systems

AMD is looking for a talented leader to help develop innovative debug solutions and related features, bring up new products, and improve the quality of our existing debug solutions. As a team leader, you will play an essential role in enhancing AMDs capacity to deliver the highest quality and industry-leading system-level debug technologies to the market. THE PERSON: We are looking for a hands-on leader who will be responsible for leading the team, planning IP, software and systems development projects, creation of documentation, and delivering software products for internal as we'll as external customers. This role also requires that the individual can interact and work with their counterparts globally to ensure effective delivery of the projects. The ideal candidate embodies a problem-solving mindset and demonstrates exceptional software engineering skills and system debugging expertise. They are driven by a passion for creating innovative tools that tackle complex system-on-chip (SoC) design challenges. As a member of the ChipScope team, the candidate will take on the rewarding challenge of addressing intricate SoC and FPGA in-system debug issues, developing user-friendly tools that enhance productivity. The team plays a crucial role in every stage of product development from design to prototyping, implementation, and testing. Successful candidates will combine a strong understanding of computer technologies with remarkable leadership and software engineering skills, thriving in a fast-paced environment alongside diverse engineering teams. This position offers incredible opportunities for personal and professional growth in product development. KEY RESPONSIBILITIES: Participate and play critical role in planning project deliverables Own and drive software/IP/systems design, development, verification and release the product to customers Performing individual goal planning and evaluation in accordance with AMD policies Maintaining the health and morale of the team Develop and grow the engineering skills of the team Drive critical issues and interface with cross functional teams Provide periodic management/executive updates Lead brainstorming sessions PREFERRED EXPERIENCE: Experience in a hands-on software engineering, development, and/or architectural leadership role Solid knowledge of software and systems design fundamentals Strong Python and C/C++ programming skills and Linux and Windows operating system knowledge Embedded Programming knowledge and skills desired Experience with FPGAs and Adaptive SoCs desired Consistent record in engineering execution, delivery software on time with high quality and achieving premium high-performance software solutions Proven track record of planning and delivering complex system software products. Experience leading multiple projects with competing priorities Strong project management skills and experience with project management techniques such as scheduling, budgeting, and risk management Disciplined approach to problem solving and ability to make business decisions in a technical environment Strong Interpersonal, verbal, and written skills Self-motivated with an ability to multi-task ACADEMIC CREDENTIALS: bachelors or masters degree in Computer/Software Engineering, Computer Science, or related technical discipline s

Education: BE/BS/Mtech/M.E degree in Electrical/Electronics/Computer science from a reputed institute Responsibilities: Translate requirements to design specification by working closely with system architects Translate the design specification to optimal digital micro-architecture RTL coding using Verilog and System Verilog Building reusable sub-systems and systems, and drive automation with hands-on contribution during the integration of IP Manage the complexity of Safety, Security and Low-power as overlays on vanilla sub-system architectures Continuously improve the development and support model employed on Digital Processing sub-systems to ensure a high level of scalability and efficiency in product engagements Support simulation, DFT and silicon verification and validation of sub-systems, test and evaluation of ASIC products and FPGA development systems Meet power, performance and area goals by micro-architecture optimization Work closely with DV team to develop test-plans Front end implementation - Lint/CDC , synthesis, Timing constraint development Work closely with DFT and PD teams for signoff Support Silicon validation Mentor junior design engineers Minimum Qualifications: BE/BS/Mtech/M.E degree in Electrical/Electronics/Computer science from a reputed institute 10 years of relevant experience Strong engineering background in embedded system design, including ASIC microarchitecture, computer architecture, SoC architecture, and custom or standard DSP or hardware accelerator microarchitecture Strong hands-on RTL coding experience and debugging skills Digital Subsystem, clocking and full chip integration experience Expertise in timing constraints development and critical path timing closure Experience with silicon and software product development and understanding the product development lifecycle Knowledge of industry standard bus protocols such as AHB, APB, AXI Experience in digital signal processing and Matlab modeling is highly desirable Excellent verbal and written communication skills to work effectively with teams spread geographically Experience in mentoring junior engineers

Education: BTech/MTech degree in Electrical/Electronics/Computer science from a reputed institute Job Responsibilities: Translate requirements to design specification by working closely with system architects Translate the design specification to optimal digital micro-architecture RTL coding using Verilog and System Verilog Continuously improve the development and support model employed on Digital Processing sub-systems to ensure a high level of scalability and efficiency in product engagements Support simulation, DFT and silicon verification and validation of sub-systems, test and evaluation of ASIC products and FPGA development systems Meet power, performance and area goals by micro-architecture optimization Work closely with DV team to develop test-plans Front end implementation - Lint/CDC , synthesis, Timing constraint development Support Silicon validation Job Requirements: BTech/MTech degree in Electrical/Electronics/VLSI with 3-6 years of experience from reputed institutes Strong hands-on RTL coding experience and debugging skills Expertise in timing constraints development and critical path timing closure Coding up in C tests on M3 Series Cortex based products. Expertise in automation and scripting languages like Perl, Python, and shell scripting Proficient in Version control systems, such as Perforce, SVN, SOS Proficient in Verilog, System Verilog and UVM Ability to manage multiple tasks and work effectively in a fast-paced environment Able to communicate effectively

Dear, Hope you doing great! Have an opening for below mentioned role with Leading Electronic ,Defense, Aerospace company Location: Hyderabad ( If interested & ready to relocate pl apply) (This is an urgent requirement immediate availability is highly desirable) Job Opportunity: Software Defined Radio (SDR) Developer Location: Hyderabad Industry: Electronics / Telecommunications (Preferred ) Qualification: B.Tech / M.Tech (ECE preferred) Notice Period - Immediate joiner / 15 days Are you passionate about building next-generation wireless communication systems? Join our team as an SDR Developer and work at the forefront of software-defined radio and embedded systems technology. Role Overview: We are looking for a talented and driven Software Defined Radio (SDR) Developer to contribute to the design and development of advanced wireless communication systems. The ideal candidate will have a solid foundation in digital communication, FPGA/SoC platforms, and SDR frameworks. Key Responsibilities: Implement channel coding and decoding algorithms in digital communication systems. Develop and simulate digital modulation techniques such as BPSK, QPSK, 8PSK, and QAM. Design and simulate digital filters (FIR/IIR) for baseband signal processing. Port applications on PetaLinux using platforms like Zynq Ultrascale and Kria SoM . Work on system design and development using FPGA, DSP, and ARM processors . Apply SCA (Software Communications Architecture) standards in SDR applications. Collaborate with teams on the implementation of physical layer components for wireless systems. Develop designs using Verilog and integrate with SoM (System on Module) and SoC (System on Chip) technologies. Required Skills: Strong knowledge of wireless communication systems and modem design . Hands-on experience with FPGA programming , especially using Verilog . Practical experience with Zynq Ultrascale , Kria SoM , or similar embedded platforms. Familiarity with SDR development environments , PetaLinux , and signal processing techniques. Experience with SoM/SoC architectures and real-time embedded development. Understanding of SCA standards is a plus. If interested, kindly revert with updated CV mentioning below details on preksha@topgearconsultants.com for more company details. Pl share your resume; Mentioning BELOW DETAILS mandatory Current Location Preferred Location Highest Qualification: Years of Exp Current Salary Expected Salary Notice Period Regards, preksha shanbhag Visit us at www.topgearconsultants.com www.linkedin.com/in/preksha -shanbhag-64b284272

As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL/Test Pervassive Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -8+ years of relevant experience - At least 1 generation of processor core/cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

Candidate should have experience in Software development, tools development role, firmware development role or validation tools development.Candidate shall design and develop algorithms for Post Silicon Validation of next generation IBM server processors, SOCs and ASICs. He/She will be working on processor Bringup Activities and own key debugs during the bring up/power on phase. The candidate will be expected to interface with multiple stakeholders in hardware design teams, lab teams, performance teams and characterization teams. Candidate must work on coverage closure by developing comprehensive test plans and strategies and drive to achieve coverage goals while interacting with stakeholders, verif teams and design teams. He/She must be skilled in utilizing object-oriented programming skills in C/C++ and scripting languages like Python/Perl to write complex test scenarios to automate/optimize. Candidate must possess experience in verifying multi-processor cache coherency and memory subsystems, ensuring seamless operation in complex systems. Proficiency in emulator env/FPGA validation is preferred. She/he must possess excellent communication skills and understand agile processes. The candidate must have an eagerness and curiosity to learn and be willing to code and participate hands on. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Technical ExpertiseVery proficient in C programming, Strong Scripting skills. Over 5 years experience in hands on Software development using C, C++. Computer Architecture KnowledgeIn-depth knowledge of computer architecture, including processor core design specifications, instruction set architecture, and logic verification. Multi-Processor Cache CoherencyExperience in verifying multi-processor cache coherency and memory subsystems, ensuring seamless operation in complex systems. Operating Systems and ConceptsAtleast 2 years experience with Multithreading, context switching, memory management related development Preferred technical and professional experience IO device drivers, firmware exposure(NIC controller, PCIe device controllers, ASIC FW development experience) ARM architecture RISC V architecture Spike simulator experience, QEMU simulator