About The Role RTL design for 3D Graphics Fixed Function components. Develops the logic design, register transfer level (RTL) coding, and simulation for graphics IPs (including graphics, compute, display, and media) required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly across verification hierarchies, drives unit level verification, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure highquality integration of the GPU block. Must Have Skills IP RTL design, graphics domain, GPU RTL, micro-architecture, system verilog, AI will be a plus. Qualifications You must possess a minimum of bachelor's degree / MS degree in Computer Engineering, Computer Science or Electrical Engineering with 8+ years of industry experience. Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies"”spanning software, processors, storage, I/O, and networking solutions"”that fuel cloud, communications, enterprise, and government data centers around the world.

About The Role Conducts verification of IP and/or SoC microarchitecture using formal verification tools, methodologies, and technologies based on model checking and equivalence checking algorithms. Creates comprehensive formal verification test and coverage plans including definition of formal verification scope, strategy, and techniques. Creates abstraction models for convergence on the design, carves out the right boundaries for the design, and tracks, verifies, and applies abstraction techniques. Develops formal proofs to implement the verification plan, reviews the completed proofs, and develops new formal verification methodologies. Performs convergence on design by creating formal verification methodology, abstraction, and simulation techniques. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications: 5+ years of experience in the verification of IPs Hands on experience in applying formal property verification for Ips signoff at least for 3 years Hands on experience in resolving convergence issues using FV on multiplies Managing and Guiding juniors in their verification task, Stakeholder management. Preferred Qualifications: Expertise in FV verification planning and strategies Good understanding of FV tools and capabilities Inside this Business Group In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations. DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Greetings From Dexcel Designs! We are inviting applications for FPGA Design and Verification Engineer Job Overview: We are seeking FPGA Design and Verification Engineers with 3-6 years of experience in RTL design, FPGA verification, and high-speed interface development . This role involves designing, implementing, and validating FPGA-based systems while working closely with cross-functional teams in hardware and embedded software development. Key Responsibilities: Develop and implement RTL designs for FPGA-based systems. Perform functional verification and validation of FPGA designs. Work on timing analysis, synthesis, and debugging of FPGA architectures. Collaborate with hardware, embedded software, and system architects to ensure seamless integration. Debug FPGA designs using industry-standard tools and methodologies . Technical Skills Required: Strong understanding of RTL design (Verilog/VHDL) and FPGA implementation. Experience with FPGA tools such as Vivado, Quartus, Synplify, ModelSim, and QuestaSim . Hands-on experience with at least one of the following high-speed interfaces : PCIe, SATA, USB, DisplayPort, JESD204B, SRIO MII/RMII/GMII/RGMII/SGMII/XAUI/RXAUI DDR/LPDDR/DDR2/DDR3, QDR memories Knowledge of FPGA debugging techniques, timing closure, and constraint handling . Preferred Skills: Experience in FPGA-based hardware design and testing . Exposure to SoC architectures and system-level integration . GFPGA Design and Verification Engineer ) and power integrity (PI) analysis .G

Greetings from Dexcel Designs! Inviting applications for the Hardware Engineer Board Design / Circuit Design position Job Summary We are looking for a Hardware Design Engineer with 3-8 years of experience in designing embedded systems and high-performance electronics for defence, aerospace, and industrial applications . The role involves circuit design, PCB development, and system integration for platforms such as RFSoC, Agilex, Intel, TI, and AD processors/SOCs while working with industry-standard VPX, 3U, 6U, or custom form factors . Key Responsibilities Design and develop digital, analog, and power supply circuits for embedded systems. Work with high-speed and parallel interfaces including PCIe, JESD204B, Ethernet (1G/10G), USB, DDR3/DDR4, SPI, and I2C . Implement serial and parallel interfaces such as LVDS, SRIO, MIPI, and SATA/NVMe storage solutions . Develop schematics and PCB layouts , ensuring signal integrity, power integrity, and thermal efficiency . Design hardware using VPX, 3U, 6U, and custom form factors . Perform board bring-up, validation, and debugging using lab tools like oscilloscopes and logic analyzers. Ensure compliance with EMI/EMC standards, MIL-spec requirements, and ruggedized hardware designs . Collaborate with cross-functional teams including FPGA, Embedded Software, and System Engineers for seamless integration. Required Skills Strong understanding of PCB layout, power distribution, and high-speed signal design . Hands-on experience with schematic capture and PCB design tools (Allegro, Altium, or similar) . Knowledge of real-time embedded architectures and processor-based system design. Experience with board-level debugging, hardware validation, and compliance testing . Preferred Skills Experience with FPGA-based designs (Xilinx, Intel, Lattice) . Exposure to AI/ML accelerators, high-speed data converters, and RF front-end systems . Understanding of thermal management and ruggedized hardware design

Greetings from Dexcel Designs! We have an exiting position for Engineering Manager. Job Overview: We are seeking an Engineering Manager with experience of 12+ years in Defense and Avionics projects to lead and coordinate cross-functional teams working on FPGA, hardware design, embedded systems and mechanical teams . The ideal candidate will be responsible for project planning, execution, and timely delivery , while ensuring adherence to industry standards and processes. This role requires strong leadership, client coordination, and technical oversight to drive successful project outcomes. Key Responsibilities: Project Management & Execution: Develop detailed project plans , define milestones, and ensure on-time deliveries. Track project progress, mitigate risks, and drive issue resolution. Ensure compliance with Defenceand Avionics industry standards . Team Coordination & Leadership: Lead and coordinate hardware, FPGA, and embedded software teams . Foster a collaborative environment to improve efficiency and innovation. Client & Stakeholder Management: Serve as the primary point of contact for clients, management, and stakeholders . Communicate project updates, risks, and solutions effectively. Process & Compliance: Implement and oversee engineering processes, quality standards, and documentation . Ensure adherence to industry best practices for defenceand avionics product development . Drive continuous improvement initiatives within the engineering teams. Required Skills & Expertise: Strong experience in planning, execution, and project delivery for defenceand avionics systems . Knowledge of hardware design, FPGA, embedded systems, and high-speed interfaces . Experience in DO-254, DO-178C, MIL-STD, and other defenceindustry standards . Strong understanding of risk management, issue tracking, and resource planning . Excellent client communication, negotiation, and stakeholder management . Experience with agile methodologies, project tracking tools (JIRA, MS Project, etc.) . Preferred Skills: Background in defenceelectronics, avionics LRUs, or mission-critical embedded systems . Exposure to PCB design, FPGA development tools, and embedded software workflows .

Technical Expertise - Solid understanding of computer architecture and digital systems RTL code for IP, sub-systems, and SoCs. - Proficiency in hardware description languages (HDLs) such as Verilog or system Verilog -Experience in building emulation model builds from scratch for SoC components - Familiarity with emulation platforms and tools (e.g., Cadence Palladium, Mentor Graphics, Synopsys ZeBu). including model compilation, test execution, and debugging - Knowledge of FPGA (Field-Programmable Gate Array) technology, including synthesis, implementation, and debugging. - Experience in setting up and configuring emulation environments. - Ability to manage emulation servers, clusters, and resources effectively. - Knowledge of software tools used in conjunction with emulation (debuggers, performance analyzers, test automation frameworks). - Ability to develop and execute verification plans specific to emulation environments - Protocol knowledge of peripherals: Proficient in Arm CPU cores and PCIe Gen4/5, JTAG, SPI, UART, I2C, USB2.0, USB3.0, Display Port, HDMI, Ethernet 1G/2,5G/5G/10G - Experience in XTOR Integration and a hands on experience on Speedbridges and Vrtual Bridges is a plus. Scripting and Automation - Proficiency in scripting languages Unix, Python, Perl, Tcl for automation of emulation tasks, test case generation, and results analysis. - Experience in developing automated flows for regression testing and continuous integration (CI) pipelines.

Must have exp in FPGA, VHDL, Embedded C.

Arm s hardware is at the heart of the computing and connectivity revolution that continues to transform the way people live and businesses operate. As we continue to grow, we need the best engineers to join a team responsible for the development of sophisticated Subsystems and Solutions. Soon, we could be using your talents to develop the technologies that will enable the latest compute solutions in todays Enterprise, Auto and Client markets. Responsibilities: As a verification engineer with a knowledge of subsystems and SoCs you will make valuable contributions to a team tasked with verifying the functional correctness of SoC. Engineers will have ample opportunities to collaborate with designers and architects to understand design specifications and build a functional verification strategy. Key responsibilities will include writing test plans, defining test methodologies, and completing functional verification to the required quality levels and schedules. Work with the Emulation/FPGA team in understanding various verification collaterals required for driving stimulus at the board level. Will collaborate with engineers in architecture, design, verification, implementation, modeling, performance analysis, silicon validation, FPGA and board development. Senior engineers are also encouraged to support junior members. Required Skills and Experience : 4-10 years of proven experience in working on IP/Subsystem/Soc Verification Experienced in Protocol on Flash Storage device Controller with unipro and MIPI PHY. Experience in Working on any of cross functional flows like Reset, Ras(Error and Interrupt), Security, low Power for High-speed IO IPs. Good Skills in System Verilog, shell programming/scripting (e.g. Tcl, Perl, Python etc.) Experienced in one or more of various verification methodologies UVM, formal and low power. Exposure to all stages of verification: requirements collection, creation of test plans, testbench implementation, test cases development, documentation, and support. Experience with various front-end verification tools - Dynamic simulation tools, Static Simulation tools and Debuggers. Nice To Have Skills and Experience : Possess knowledge of object-oriented programming concepts Practical experience of working on Processor based system design Experience in Server/ Infrastructure SoC Strong understanding of CPU Architecture / micro-architectures! In Return: Partner and customer focus Collaboration and communication Creativity and innovation Team and personal development Impact and influence Deliver on your promises

This position is part of Seagate Research Group (SRG). Seagate delivers advanced digital storage solutions to meet the needs of today s consumers and tomorrow s applications. Through technology, leadership and innovation, Seagate continues to help individuals and businesses maximize the potential of their digital content in an ever-evolving, on-demand world. About the role - you will: Work full time on projects at Pune in assisting Seagate Research Architect/leads in the area of most cutting-edge research in storage technologies Responsible for investigating emerging technologies in storing data efficiently, which create data in new frontiers from AI/ML/mobility. Potentially explore new mechanisms in electronic hardware modeling and prototyping in processing the data using upcoming technologies such as computational storage securely. Your work includes but would not be limited to, survey and process public and enterprise forums to help build models around these technologies, generate new ideas and conceptualize them and with the help of senior engineers in the team, contribute in the development of architecture towards building proofs of concepts. Research/investigate emerging technologies in storage components and system, Data creation models and storage security Document current and future storage architectures for different applications Provide research intelligence for future Seagate products or create reference architectures Work with subject matter experts at all Seagate (worldwide) sites Create internal and external research papers and work with your affiliated school to bring academic research in these areas for applications in storage industry About you: Creative, independent and self-starter individual with excellent written and interpersonal communication who would be looking forward to work in corporate set up Must be authorized to work in India while pursing education Teamwork is a core competency at Seagate, individual must be able to work and communicate effectively with a diverse group of engineers Must have demonstrated ability to study a functional area in depth Ability to present to colleagues and partner Your experience includes: Working knowledge of Unix-based and Windows Operating Systems Graduate School Research level experience with innovative techniques in AI/ML as well as Exposure to storage domain and FPGA based systems are added plus Location: Pune, India Our site in Pune is dynamic, both in our cutting-edge, innovative work, as well as our vibrant on-site food, and athletic and personal development opportunities for our 400+ employees. You can enjoy breakfast, lunch, or dinner from one of four cafeterias in the park. Take a break from your workday and participate in one of our many walkathons or compete against your colleagues in carrom, chess and table tennis. Learn about a technical topic outside your area of expertise at one of our monthly Technical Speaker Series, or attend one of the frequent on-site cultural festivals, celebrations, and community volunteer opportunities. Location : Pune, India Travel : None

There is energy here energy you can feel crackling at any of our international locations. It s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on RD, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a team first organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you re looking for.Responsibilities Skills We are seeking a highly motivated Staff design engineer who will be responsible for design and development of RTL for Machine Learning engine. You are responsible to implement ML operators efficiently using resources on low power FPGA. You need to bring experience in optimizing data path for high throughput and low latency. Good understanding of neural network accelerators and/or DSP processors is essential to be successful in this job. Requirements Key Skills In-depth experience in designing and developing RTL using Verilog, System verilog-HDL. Ability to carry out functional simulation using industry standard simulation tools. Good understanding of ML operations like convolution, BatchNorm etc Experience in image processing and DSP algorithms implementation Deep understanding of machine learning, data models to optimally map it with hardware. Experience in FPGA/ASIC synthesis flow, timing closure. Working knowledge of computer architecture and memory management Experience with C and/or SystemC is a plus Education and General: BE/MTech/PhD in Electronics, Electrical or Computer Engineering Minimum of 10 years (8 year for MTech and 5 years for PHD) experience in RTL design Independent and self-motivated, capable of executing under dynamic environment and uncertainties Innovative, problem solver who likes to come up with newer and better solutions for existing problems Good cross team communication and technical documentation desire

There is energy here energy you can feel crackling at any of our international locations. It s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on RD, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a team first organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you re looking for.Responsibilities Skills Lattice Semiconductor is seeking a Principal to join the HW design team focused on IP design and full chip integration. This position is an opportunity to be part of a dynamic team with ample opportunity to contribute, learn, innovate and grow. Role specifics: This is a full-time Principal Engr position located in Pune, India. The role will focus on FPGA projects concentrated in Pune and similar time zones. The qualified candidate will lead the design and development of complex components of FPGA, ensuring they meet performance, power, and area targets The qualified candidate will be expert in driving Subsystem development and ensure design meets high standards of quality and reliability, conduct regular reviews and audits The role requires working closely with architecture team to define micro architect and design spec Serve as a technical expert in SoC design, providing guidance and support to other engineers. The successful candidate will be open and willing to both (a) teach best-known-methods to an existing FPGA team and (b) learn from the team about the complications of highly programmable FPGA fabrics. This role carries the need to be both a strong educator and a open-minded student. Accountabilities: Serve as a key contributor to FPGA design efforts. Drive logic design of key FPGA system full chip and bring best-in-class methodologies to accelerate design time and improve design quality. Ensuring design quality throughout project development conducting regular reviews and audits Work with cross functional team including program management, package design, pre and post silicon validation to drive the program Develop strong relationships with worldwide teams. Drive continuous improvement initiatives, staying up-to-date with the latest industry trends and technologies Occasional travel as needed. Required Skills: BS/MS/PhD Electronics Engineering, Electrical Engineering, Computer Science or equivalent. 15+ years of experience in driving logic design across a multitude of silicon projects. Expertise in SoC integration, defining micro-architecture and experience of selecting 3rd party IP. Expertise in working with ARM processor, AXI, AMBA bus, ENET, PCIE, USB, safety and/or security protocols, debug architecture. Experience in leading the project through out design cycle and working with cross organization Familiarity with FPGA designs, use-cases, and design considerations is a plus. Proven ability to work with multiple groups across different sites and time zones. Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 800 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA , CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com . You can also follow us via Twitter , Facebook , or RSS . At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates. Lattice Feel the energy.

Job Description Danfoss is looking for an experienced person having solid experience in Embedded Systems Software Testing using LabVIEW and TestStand, in accordance with Software Testing Life Cycle. This person will be responsible to guide and coach the team as well as independently write test cases and develop scripts based on defined software requirements . Job Responsibilities Responsibilities for this position include, but are not limited to, the following. Writing Software testcase specification and management Scripting the test cases per test case specification Testing, test executing and reporting Leading and coaching the team Background Skills Education B.E/B. Tech/M.Tech/Master (Electronics / Telecommunications / Computers Science)OR equivalent Certified LabVIEW Developer (CLD) is must Certified LabVIEW Architect(CLA) is preferred Experience Attributes 5 or more years of experience in Embedded software testing using LabVIEW and NI Test Stand Creating Test strategie Must have specialized knowledge LabVIEW, LabVIEW Realtime and FPGA NI TestStand Understands CAN Communication Protocols like UDS, KWP2000, CANopen and J1939 Test Specification Management Tools like Polarion or Equivalent Change Management Tools like JIRA/VSTS Version control Tools like SVN/GIT/Clearcase Understands Traceability management Tools like Reqtify or equivalent Understands Software Architecture Design Software Test Life Cycle Employee Benefits We are excited to offer you the following benefits with your employment: Bonus system Paid vacation Flexible working hours Possibility to work remotely Pension plan Personal insurance Communication package Opportunity to join Employee Resource Groups State of the art virtual work environment Employee Referral Program This list does not promise or guarantee any particular benefit or specific action. They may depend on country or contract specifics and are subject to change at any time without prior notice. Danfoss Engineering Tomorrow At Danfoss, we are engineering solutions that allow the world to use resources in smarter ways driving the sustainable transformation of tomorrow. No transformation has ever been started without a group of passionate, dedicated and empowered people. We believe that innovation and great results are driven by the right mix of people with diverse backgrounds, personalities, skills, and perspectives, reflecting the world in which we do business. To make sure the mix of people works, we strive to create an inclusive work environment where people of all backgrounds are treated equally, respected, and valued for who they are. It is a strong priority within Danfoss to improve the health, working environment and safety of our employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, veteran status, or other protected category.

UST Designation: Lead I - Semiconductor Product Validation Requirement name: Cluster Validation Engineer Role Proficiency: Independently handle test deliverables and deadline management coordinate with and build the team for a given project Outcomes: Work with customer to ensure there are no escalations Coordinate with the team effectively Conduct technical interview for the project requirements Perform validation and root cause analysis Perform escape analysis Isolate/ packetize the failures to correct component Attend customer meeting and communicate effectively on the requirements/ results. Locate the product failures and report it in test repository and bug tracker Learn technology business domain system domain individually and as recommended by the project/account Complete the certifications for the role (like ISTQB UST GAMMA certifications) Ensure the product and validation complies with the defined SLA Measures of Outcomes: Perform defect triaging Adherence to schedule and timelines Number of post delivery defects Number of non-compliance issues SLA turnaround of production bugs Define productivity standards for project Completion of all mandatory training requirements Outputs Expected: Manage Project: Manage task deliverables with quality and targeting completion timeframe. Estimate: Estimate time effort and resource dependence for ones own work and for others work. Document: Create component level / product behaviour documents Create test reporting templates BKMs and knowledge sharing documents for team Status Reporting: Report status of tasks assigned Compliance with validation standards and process Mentoring: Mentor senior validation engineers by providing on job facilitations Host classroom training sessions for the junior validation engineers Skill Examples: Good presentation skills and diplomacy Should possess good bug advocacy skills Automation scripting skills Able to perform severity and priority identification of sightings raised Ability to estimate effort time required for own work and for the junior engineers Ability to perform and evaluate test in the customer or target environment Work in a team environment Good written and verbal communication abilities Good analytical skills Knowledge Examples: Able to understand the product lifecycle and deadline Should possess excellent domain knowledge Good CPU/ GPU architecture knowledge Possess very good knowledge of the product Additional Comments: Client job title: Firmware Validation Engineer UST Job Title: Lead I - Semiconductor Product Validation Who we are: At UST, we help the world s best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in over 25 countries, we build for boundless impact touching billions of lives in the process. Visit us at UST.com. The Opportunity: UST is looking for 1 Semiconductor Product Validation Engineer. Key Roles Responsibilities: We are looking for a highly motivated Senior Software Engineer with experience in System on Chip Architecture (SoC), Bring up of SoC, root causing issues at the intersection of multiple subsystems across firmware and hardware. Responsibilities: Owns SOC and Platform FW Integration, validation (including validation environment), and debugging of different domains within server architecture (such as SoC FWs, BIOS, BMC etc.) Ability to see system level big picture to validate that the integrated firmware/system software aligns to architectural goals of product to meet the defined use cases and KPIs (thermal, power, stability and performance). Collaborate with system and FW architects to gather the requirements, translate to validation plans, develop test content, automate executions, and debug/triage of observed/reported failures. Excellent debugging and troubleshooting skills with the aim to become point-of-contact for platform level issues. Ensure systematic closure of issues for subsequent releases. Work with architect, firmware, program management and component dev teams for day-to-days operations as well as for long-term roadmap improvements by feeding back key learnings Passionate about exploring and deploying noble methods to improve test coverage, release/test automation, and efficiency of our FW releases. Create automated dashboards to always reflect health and quality of system for decision making. Required Skills: Demonstrated experience in system level Integration, validation (including validation infrastructure setup), automation framework (such as Robot Framework), and debugging of system software. Experience in validation / development in server space is big plus. Experience of creating validation test plans, developing test content to achieve the validation plan, and automating the execution of test contents. Experience of creating or working with automated testing pipeline aka CI/CD (integration + validation) Firmware development and testing on multiple HW test environments (FPGA, Emulation, Simulation etc.) Have deep experience of system level debugging (including customer issues) with good understanding of managing and triaging production level issues. Good knowledge of hardware debuggers like JTAG, Oscilloscope, and Logic Analyzer etc. Knowledge of automation framework setup and deployment. Excellent communication and inter-team collaboration skills Debug experience resulting in solving complex Hardware/Firmware interface issues. Qualification: Bachelor s or higher in Computer Science, Computer Engineering, Electronics Engineering, or similar. 8+ years of professional experience in testcase design/development, test automation, integration, validation, or system level debugging in embedded systems Strong problem solving, debugging, and troubleshooting skills. Hands on experience in programing in Python or C or C++ Experience with Platform initialization, Board support package (UEFI/U-Boot), integration, low level drivers for peripherals such as PCIe, I2C, eMMC, SPI, USB, UARTs as well as Memory Management, Scheduling, Interrupts, and multi-threading. What we believe: We re proud to embrace the same values that have shaped UST since the beginning. Since day one, we ve been building enduring relationships and a culture of integrity. And today, its those same values that are inspiring us to encourage innovation from everyone to champion diversity and inclusion and to place people at the centre of everything we do. Humility: We will listen, learn, be empathetic and help selflessly in our interactions with everyone. Humanity: Through business, we will better the lives of those less fortunate than ourselves. Integrity: We honour our commitments and act with responsibility in all our relationships. Equal Employment Opportunity Statement UST is an Equal Opportunity Employer. We believe that no one should be discriminated against because of their differences, such as age, disability, ethnicity, gender, gender identity and expression, religion, or sexual orientation. All employment decisions shall be made without regard to age, race, creed, colour, religion, sex, national origin, ancestry, disability status, veteran status, sexual orientation, gender identity or expression, genetic information, marital status, citizenship status or any other basis as protected by f

Key Responsibilities: 1. Port ASIC designs to Xilinx FPGA platforms while ensuring performance and area efficiency. 2. Develop and optimize RTL (Verilog/VHDL) to meet FPGA design constraints. 3. Perform timing closure, static timing analysis (STA), and floorplanning. 4. Utilize Xilinx FPGA tool flow (Vivado) for synthesis, implementation, and bitstream generation. 5. Debug and validate FPGA implementations using simulation, hardware testing, and debugging tools (Chipscope, SignalTap, etc.). 6. Optimize FPGA performance through placement, routing, and power optimizations. 7. Collaborate with ASIC and system engineers to ensure seamless integration. 8. Good to have experience with Synplify for synthesis. 9. Experience with scripting languages (Tcl, Python, Perl) for automation is a plus.

Job Responsibilities 1. Understand and Participate in Establishing Requirements Gain a deep understanding of system-level requirements impacting firmware deliverables. Actively participate in the creation of firmware requirements based on system specifications. Collaborate with the broader team to define and improve system-level requirements for hearing aid firmware. Align firmware design with requirements through continuous exploration of the firmware system, review of documentation, and consultations with senior team members. 2. Design and Implement High-Quality Firmware Create designs that meet firmware requirements. At this level, the engineer is expected to solve moderate technical challenges. Senior engineers review solutions for technical sound. Document and review designs, ensuring they provide value and enhance understanding of the firmware. Apply programming knowledge (e.g., C, assembly) to implement firmware on resource-constrained hardware. Follow best practices in firmware development processes such as code reviews, design documentation, and adherence to coding conventions. Update the status of assigned tasks using established issue and project tracking software. Use version control systems to manage code effectively. Investigate, root cause, and resolve firmware issues promptly, providing feedback on potential solutions and their impact to the firmware management team. 3. Verify Firmware Functionality Support the Firmware Verification Team in developing test plans and executing tests to ensure firmware meets high-quality standards at the system level. Review test plans and provide constructive feedback. Conduct unit tests to verify the functionality of developed firmware before passing it to the verification team. Collaborate with Firmware Verification Engineers and others in R&D to identify and resolve issues. 4. Participate Effectively in Project Activities Understand and follow established organizational processes such as Advanced Development and Product Development processes. Work with the Firmware Project Sponsor/Manager to create project plans and provide work estimates for project milestones. Take proactive ownership of project assignments and follow the project management process (Scrum) for assigned projects. Communicate changes to work effort estimates and their potential impact on the project schedule. Provide updates on project activities during sprint reviews, stand-up meetings, and one-on-one meetings. Job Requirements Education and Experience: Education: Bachelors or Masters degree in Electronics and Communication, Computer Science, Embedded Technology, or a related field. Experience: 4-8 years of relevant experience with a BS degree 0-4 years of relevant experience with an MS degree Knowledge and Technical Requirements In-depth knowledge in one or more of the following domains is required: Digital Signal Processing (DSP) Real-time Signal Processing: Knowledge of hardware or embedded systems for real-time signal processing, including the use of microcontrollers, DSP chips, and FPGA. Filtering: Designing and implementing digital filters (FIR, IIR) to remove noise, smooth, or enhance signals. Knowledge of filter design tools and techniques (e.g., Butterworth, Chebyshev filters). Convolution & Correlation: Understanding how to apply these operations to signals to filter or detect patterns. Fourier Analysis: Applying Fourier transforms (FFT, DFT) to analyze signals in the frequency domain, including spectral analysis and signal reconstruction. Time-Frequency Analysis: Familiarity with techniques like Short-Time Fourier Transform (STFT) or wavelet transforms for analyzing non-stationary signals. Adaptive Filtering: Understanding algorithms that adapt their characteristics based on the signal's input, such as LMS (Least Mean Squares) and RLS (Recursive Least Squares). Signal Compression & Coding: Knowledge of data compression techniques (e.g., JPEG, MP3) for efficient transmission and storage of signals. Embedded DSP Experience in implementing DSP algorithms on embedded systems, such as using ARM, TI processors or specialized DSP hardware. Real-Time Operating Systems (RTOS): Experience with real-time operating systems, such as FreeRTOS, VxWorks, or other embedded OS, for scheduling and task management. Hardware/Software Interface: Experience interfacing with hardware components (ADC, DAC, sensors, actuators, etc.). MATLAB/Simulink: Ability to model and simulate DSP algorithms using tools like MATLAB and Simulink. Embedded Development Tools: Familiarity with IDEs (e.g., Eclipse, Keil, IAR Embedded Workbench) and debugging tools (JTAG, oscilloscopes, logic analyzers). Machine Learning (ML) & AI Integration DSP and Machine Learning: Integrating machine learning with DSP to enhance signal processing tasks such as classification, pattern recognition, and feature extraction. Deep Learning for DSP: Familiarity with neural networks, CNNs (Convolutional Neural Networks), RNNs (Recurrent Neural Networks), GANs (Generative Adversarial Networks), and other deep learning architectures. Proficiency in using TensorFlow, PyTorch, and Keras Wireless and wired communication protocols. Firmware testing methodologies and tools Proficiency in programming languages such as C or assembly. Familiarity with scripting languages like MATLAB or Python. Understanding of analog and digital circuitry. Competencies, Skills, and Abilities Strong verbal and written communication skills. Driven, methodical, and detail oriented. Ability to work both independently and as part of a team. Proficiency in problem-solving.

InnoPhase Inc., DBA GreenWave Radios, is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays. Based in San Diego, California, GreenWave Radios has earned a reputation for delivering power-efficient digital-to-RF solutions. Our commitment to innovation is backed by a robust team of more than 100 talented engineers spread across four R&D facilities worldwide and an extensive portfolio of over 120 global patent filings, underscoring our dedication to pushing the boundaries of radio technology. InnoPhase Inc., DBA GreenWave™ Radios and Synergic Emergence have a co-employment relationship. For over three years, GreenWave Radios has partnered with Synergic Emergence, a professional employment organization provider, to offer our employees the best benefits and services. This arrangement means that Synergic Emergence provides employee pay checks and benefits, and GreenWave Radios will provide employment, evaluation, and advancement. By outsourcing some HR functions, GreenWave Radios can focus on what we do best – developing and implementing highly innovative SOC cellular radio integrated circuit products. Key Responsibilities: Individual contributor to develop Embedded Linux-based SW solutions for O-RAN Cellular base station radios. Design and implement Front Haul Gateway on FPGA and Network Processor-based SoCs. Assist with the definition, development & verification of FW/SW products. Establish unit level design, implementation & test strategies. Support integration & test and debug software for timely closure Work with the Applications team and customers to provide the necessary support. Job Requirements: 5+ years relevant work experience required. BE/B.Tech, M.Tech – EC/CS required. Strong coding skills in C, C++, and/or Python. Experience with Embedded Linux Kernel, Driver & Application development. Cellular RAN development experience. Experience building and integrating SW for a multi-vendor environment e.g., some internal custom SW + Xilinx IP + 3rd-party / open-source SW. Experience with ARM or similar embedded SoC development environment. Excellent debugging skills. Comfortable with configuration management, version control & modern software development flow (e.g., Agile). Good communication, documentation & presentation skills. Prior experience with FPGA and/or Network Processor software development. Team player with a strong sense of urgency to meet product schedules. Be able to work productively and independently. Desirable Skills: Familiarity with ORAN M/C/S/U plane. Familiarity with netconf2, netopeer2 client/server, yang, SysRepo, SyncE, PTP, eCPRI, CPRI. Experience with development for PetaLinux (Xilinx-based Linux SW package) including development workflow incorporating Xilinx Vivado & Xilinx SDK. Experience with Xilinx Zynq platform, Vivado Tools (10G Ethernet IP). Understanding of FPGA HDL (VHDL, Verilog, System Verilog) and/or FPGA PL/RTL. Experienced in RTOS principles and concepts & hands-on experience in any RTOS. Prior System on a Chip (SoC) product development experience. Good understanding of cellular wireless protocols (MAC/PHY). Experience using command-line Git, GitLab & Jira tools. Benefits: Competitive salary and stock options. Learning and development opportunities. Employer-paid health Insurance. Earned, Casual, Sick & parental leaves.

As an FPGA & Board Design Engineer, you must develop new hardware designs, including system design, CPLD/ FPGA or processor design, and board-level analog/ digital circuit design for embedded systems/ boards. You have to develop detailed specifications based on requirements and implement Hardware designs in accordance with those defined requirements and/or specifications. Your duties include Schematic design generation and entry, netlist generation, and close interaction with the CAD team for layout review and feedback. Perform simulation activities including timing analysis, behavioural, and functional simulations. Develop test benches and other test tools as needed to complete the verification of FPGA designs. Carry out proto H/W bring-up with support from firmware engineers. REQUIREMENTS B.Tech. or M.Tech. EE with 2+ years of FPGA experience including implementation, synthesis, and timing closure. Proficiency in Verilog, VHDL and System Verilog. Proficiency in Synopsys Synplify, Xilinx Vivado, ISE Hands-on with FPGA debug methodologies, such as ChipScope. Proficient in Schematic capture tools like Orcad/Altium Hands-on experience with lab debug equipment such as oscilloscopes and logic analyzers. Strong scripting skills in Perl/Python. Experience in test bench design and implementation Knowledge of high-speed interfaces including PCIe, Ethernet, and DDR3/4. Knowledge of low-speed interfaces including SPI, IIC, and UART. Knowledge and experience designing with Altera and Xilinx FPGAs. Detail-oriented individual with good interpersonal skills and excellent written and verbal communications skills.

Skills required: 1. Should have worked on USRP N310/X310 (N3xx/X3x0) 2. In-depth Knowledge of FPGA Architecture 3. Able to write own RTL custom HDL or drops in IP a) VHDL, Verilog, System,Verilog, Vivado HLS b) Xilinx IP, Vivado Block Diagram 4. Should have developed RFNoC Block 5. Have working knowledge of USRP Hardware Driver (UHD) 6. Able to write custom FPGA logic in RFNoC Blocks 7. Able to use library of existing RFNoC Blocks a) FFT, FIR, Signal Generator, Fosphor 8. Have understanding of GNU Radio interface to RFNoC Block 9. FPGA debugging and HW/SW integration 10. Thorough understanding of appropriate coding styles for FPGAs, and trade-offs for density and speed 11. In-depth knowledge of XILINX ZYNQ 71xx/pl-kINTEX-7 based RFNoC architecture is must. 12.Understand Customer requirements, define architecture and detailed design 13. Good Customer Communication Skills 14. Working knowledge of Agile.

In Asia Pacific, Optiver was one of the first global market makers to establish a presence in the region, with the incorporation our Sydney office in 1996. Since then, we have expanded our footprint by establishing offices in Taipei (2005), Hong Kong (2007), Shanghai (2012) and Singapore (2021). The business in Mumbai is newly established and deemed to be an integral part of the APAC strategy, with an anticipation of significant growth over the coming years. WHAT YOULL DO We are looking for an FPGA Development Team Lead to hit the ground running as one of the founding members of our Mumbai FPGA & low latency development team, working on Optivers execution platforms. Youll be focused on achieving best-in-market trade execution on the highly competitive Indian exchanges: NSE, BSE and MCX. But you wont be alone youll be backed by a strong collaboration with established FPGA & low latency development teams in Sydney and Shanghai plus gain exposure to the challenges in execution in Optivers global businesses including in the USA and Europe. As a leader you will have a strong relationship with internal stakeholders including the trading, risk, compliance, and research teams who will all be collocated with you in the Mumbai office. Youll define the future of our execution platform and execute that vision with your mixed team of FPGA developers and low latency software developers, and through influencing teams in the rest of the Asia Pacific region. You will also be responsible for building that team and growing your developers to reach their potential. As this is a hybrid role, youll still have the opportunity to be hands-on with some VHDL and C++. The developers in your team seek out business problems and design innovative solutions, owning their changes end-to-end including understanding the business problem, design, implementation, testing, deployment and monitoring. They are specialists in hybrid FPGA/software system design and consider which parts of the system are in the FPGA or in software. Our development is often fast paced, fulfilling and rewarding, with the ability to work on features and see them running in production within days. Other responsibilities include: Build and run a high performance mixed FPGA development & low latency software development team, including managing performance, career development and delivery. Define the architecture of our ultra low latency trading stack in collaboration with other senior developers. Contribute to the vision and strategy for Optivers Asia Pacific execution capability. Implement and/or build solutions to enable our low latency trading and make Optiver number one status in Indian markets. Work with stakeholders across the business in a highly collaborative, flat structure. Own the automated trading risk of our ultra low latency trading system, defining standards and practices to manage return on risk. WHO YOU ARE We need our next FPGA Team Lead to be someone with: 5+ years experience in FPGA development in financial services/capital markets. Experience leading and developing a team. Experience working through the full development lifecycle with responsibilities including gathering requirements, development, testing, deployment, monitoring and ongoing maintenance. You will also have experience leading projects. Proficient in one or more of the following: VHDL, Verilog, SystemVerilog. Basic skills in C++ (or something comparable) and Python. An understanding of computer networks and protocols (TCP/IP/UDP). WHAT YOULL GET You ll join a culture of collaboration and excellence, where you ll be surrounded by curious thinkers and creative problem solvers. Driven by a passion for continuous improvement, you ll thrive in a supportive, high-performing environment alongside talented colleagues, working collectively to tackle the toughest problems in the financial markets. In addition, you ll receive: Competitive remuneration, including an attractive bonus structure that is unmatched in the industry. We combine our profits across desks, teams and offices into a global profit pool, fostering a truly collaborative environment. The opportunity to work alongside diverse, intelligent, and driven peers in a rewarding environment. Ownership over initiatives that directly solve business problems. Training, mentorship and personal development opportunities Competitive benefits A work-from-home allowance and support DIVERSITY AND INCLUSION Optiver is committed to . We encourage applications from candidates from any and all backgrounds, and we welcome requests for reasonable adjustments during the process to ensure that you can best demonstrate your abilities. Please let us know if you would like to request any reasonable adjustments by contacting the Recruitment team via . You are viewing: FPGA Development Team Lead Careers Related vacancies Technology Technology Technology Technology Technology Technology Technology Technology Technology Technology

Data Dynamics is a global leader in enterprise data management, focusing on Digital Trust and Data Democracy. Trusted by over 300 organizations, including 25% of the Fortune 20, Data Dynamics is committed to creating a transparent, unified, and empowered data ecosystem. The company s AI-powered self-service data management software revolutionizes traditional data management by empowering data creators of all skill levels to have ownership and control over their data. Job Summary: We are looking for a highly skilled AI/ML Developer/Architect with 7+ years of experience in designing, developing, and deploying Machine Learning (ML) and Artificial Intelligence (AI) solutions . The ideal candidate should be proficient in Python, TensorFlow, PyTorch, and cloud platforms (AWS, Azure, GCP) and should have hands-on experience in building end-to-end AI/ML models, MLOps pipelines, and scalable AI architectures . Key Responsibilities: Design, develop, and optimize ML/DL models for real-world applications across multiple industries and use cases. Collaborate with data scientists, engineers, and stakeholders to define model requirements and success metrics. Implement, test, and deploy AI models using frameworks like TensorFlow, PyTorch, or Scikit-learn to solve complex business problems. Develop reusable model components to accelerate development and experimentation cycles. Fine-tune models for accuracy, performance, and efficiency through hyperparameter optimization and architecture experimentation. Perform regular model evaluations to assess bias, drift, and robustness to ensure fairness and reliability. Build scalable ML pipelines and deploy models using Docker, Kubernetes, and cloud services (AWS/GCP/Azure) for both batch and real-time applications. Establish automated CI/CD pipelines for model versioning, testing, and deployment using MLflow, Kubeflow, or SageMaker. Implement model monitoring, logging, and alerting to ensure continuous model performance and health checks post-deployment. Optimize AI solutions for low-latency and high-availability performance under varying workloads. Implement infrastructure as code (IaC) practices to maintain and deploy AI/ML infrastructure in a repeatable manner. Work with cross-functional teams to ensure that data security, compliance, and privacy policies are integrated into MLOps pipelines. Architect end-to-end AI/ML solutions, including data ingestion, preprocessing, feature engineering, training, and inference pipelines. Define scalable, modular, and cost-effective AI architectures that align with enterprise goals and technology stacks. Design solutions to support both on-premise and cloud-based AI workflows for flexibility and scalability. Create reusable design patterns for AI model integration with existing enterprise systems, APIs, and databases. Implement best practices for model governance, including compliance with regulatory standards, auditability, and explainability. Work with business leaders to translate strategic objectives into AI-driven initiatives and roadmaps. Work with large, complex datasets to optimize ETL pipelines for AI model training and inference. Design and build scalable data pipelines using distributed processing frameworks like Spark, Hadoop, or Dask. Collaborate with data engineering teams to enhance data accessibility, quality, and reliability for machine learning workflows. Leverage SQL/NoSQL databases and data lakes to create data schemas and structures that support efficient ML operations. Implement feature stores and data cataloging tools to streamline feature reuse and data discovery across teams. Develop and maintain data governance frameworks to ensure data security, privacy, and compliance. Stay updated with cutting-edge AI research and trends, including advancements in Generative AI, NLP, and Computer Vision technologies. Experiment with LLMs (Large Language Models) and generative AI models (e.g., GPT, Stable Diffusion) to develop innovative AI solutions. Prototype and evaluate emerging AI technologies to assess their applicability to business problems. Contribute to open-source AI/ML projects, research papers, and industry conferences to establish thought leadership. Collaborate with universities, research institutes, and external partners to foster innovation and access new AI capabilities. Identify opportunities to apply AI in unexplored areas to create competitive advantages for the organization. Required Skills & Qualifications: Proficiency in Python and key AI libraries such as TensorFlow, PyTorch, and Keras, with experience in both supervised and unsupervised learning models. Experience working with computer vision libraries like OpenCV and other image/video processing frameworks. Deep expertise in natural language processing (NLP) techniques using Transformers, BERT, GPT, and related models. Strong understanding of ML algorithms, deep learning architectures (CNNs, RNNs, LSTMs), and optimization techniques (e.g., gradient descent, hyperparameter tuning). Proficiency in at least one secondary programming language (e.g., Java, C++, or Go) to support AI integration into legacy systems. Experience with tools for model evaluation, visualization, and performance monitoring such as TensorBoard and ML visualization dashboards. Hands-on experience with Docker for containerization and Kubernetes for orchestration of scalable AI model deployments. Familiarity with web frameworks like FastAPI and Flask for serving AI models and building RESTful APIs. Experience with cloud-based ML services such as AWS SageMaker, GCP Vertex AI, or Azure ML, including managing pipelines and infrastructure automation. Expertise in using MLOps tools like MLflow, Kubeflow, or Argo Workflows for model tracking, lifecycle management, and version control. Knowledge of serverless architecture and microservices deployment strategies to optimize cloud infrastructure costs and performance. Ability to implement monitoring, logging, and auto-scaling for AI models in production environments. Expertise in working with data analysis libraries such as Pandas, NumPy, and SciPy for data manipulation and exploration. Strong experience with both SQL (e.g., PostgreSQL, MySQL) and NoSQL databases (e.g., MongoDB, DynamoDB), including data modeling for machine learning. Experience with big data processing frameworks such as Spark, Hadoop, and Kafka to handle large-scale data pipelines. Proficiency in feature engineering techniques, including categorical encoding, scaling, and dimensionality reduction for complex datasets. Familiarity with data augmentation, synthetic data generation, and model interpretability techniques (e.g., SHAP, LIME) to enhance model robustness. Understanding of data governance practices, including data lineage, security, and compliance in large organizations. Strong background in software engineering principles, including object-oriented programming (OOP), design patterns, and best practices. Proficiency with version control tools such as Git, including experience with branching strategies, pull requests, and code reviews. Experience in implementing CI/CD pipelines to automate testing, model deployment, and infrastructure updates. Ability to design scalable and modular AI/ML architectures that integrate seamlessly with enterprise applications and data platforms. Strong knowledge of API development, including RESTful API design, authentication, and performance optimization. Familiarity with infrastructure as code (IaC) tools such as Terraform, CloudFormation, or Ansible to support scalable deployment automation. Soft Skills & Others: Excellent problem-solving and analytical skills. Strong written and verbal communication skills. Preferred Qualifications (Good to Have): Generative AI, Stable Diffusion, LLMs, and multimodal AI models edge AI and hardware-accelerated ML (NVIDIA, TPU, FPGA) open-source AI/ML projects or research papers Job Details : If you re a passionate UX leader who thrives on solving complex design challenges, we d love to hear from you! Please email your resume to dd_hr@datdyn.com

We are seeking a talented and experienced Software Engineer to join our dynamic team. In this role, you will contribute to the design, development, and optimization of carrier-class networking and system software. As a key member of our engineering group, you'll work on cutting-edge technologies, collaborate with cross-functional teams, and drive impactful solutions. Responsibilities Collaborate with product managers, architects, and other engineers to define software requirements and specifications. Design, implement, and maintain networking and system software components using C and C++ programming languages. Conduct object-oriented analysis and design to ensure robust and scalable solutions. Debug complex system-level issues, leveraging your deep understanding of fundamental OS concepts (especially in Linux or similar operating systems). Participate in hardware and system-level design discussions, ensuring carrier-class software development. Work with Linux device drivers, system bring-up, and the Linux kernel. Navigate large codebases effectively, drawing from prior experience. Apply strong technical, analytical, and problem-solving skills to enhance software performance and resilience. Utilize scripting technologies and modern DevOps practices. Collaborate with cross-functional teams, including networking, embedded platform software, and hardware experts. Present technical topics articulately and confidently. Articulate design, lead development and see through the deployment of switching software for datacenter switching products. Work with product management and cross functional teams and develop detailed architectural, functional and design specifications to meet product requirements. Carry out detailed design, coding, unit and functional testing of software, fix complex defects, through entire lifecycle of the project. Lead development activity within the team, working with managers for detailed planning of tasks, setting intermediate milestones, strategizing execution. Mentor and guide junior engineers in the team for technical problem solving, and building long term expertise and competency. Work with cross functional validation and verification teams to ensure correct and complete verification of software and components, to meet real-life network deployments. Work closely with Juniper technical assistance team, for providing engineering assistance in supporting critical customer escalations. Qualifications Bachelor s or master s degree in computer science, electronics, telecommunication engineering, or a related discipline. 14+ years of experience in networking and system software development. Proficiency in C and C++ programming. Familiarity with data structures and system debugging techniques. Expertise in one or more of the following areas: Host Complex, System Peripherals & Drivers: CPU complex (x86); PCIe, SPI, I2C, MDIO; FPGA, CPLD, Flash Drivers Ethernet Interfaces (ranging from 1Gig to 400G+, including 800G, 1.6T), MacSec, Timing, Optics (SFP, QSFP, QDD, OSFP) High-speed packet forwarding with network processors, PHYs, and SerDes Strong communication skills, both written and verbal. Preferred Skills: Understanding of SONiC architecture & hands-on SONiC experience, Experience using SONiC development and integration Experience with software development for the forwarding ASICs, FPGAs, Network Processors etc

Arm s hardware is at the heart of the computing and connectivity revolution that continues to transform the way people live and businesses operate. As we continue to grow, we need the best engineers to join a team responsible for the development of sophisticated Subsystems and Solutions. Soon, we could be using your talents to develop the technologies that will enable the latest compute solutions in todays Enterprise, Auto and Client markets. Responsibilities: As a lead verification engineer with knowledge of power management flows, you will make valuable contributions to a team tasked with verifying the functional correctness of SOCs. Key responsibilities will include writing test plans, defining test methodologies, and completing functional verification to the required quality levels and schedules. Engineers will have ample opportunities to collaborate with designers and architects to understand design specifications and build a functional verification strategy. Work with the Emulation/FPGA team to understand the various verification collaterals required for driving stimulus at the board level. Collaborate with engineers in architecture, design, verification, implementation, modeling, performance analysis, silicon validation, FPGA and board development. Senior engineers are also encouraged to support junior members. Required Skills and Experience : 10+ years of proven experience in working on SoC power management verification environments! Knowledge of assembly language (preferably ARM), C/C++ and hardware verification languages (eg SystemVerilog), shell programming/scripting (eg Tcl, Perl, Python etc) and Experience in one or more of various verification methodologies UVM/OVM, formal, low power. Exposure to all stages of verification: requirements collection, creation of test plans, testbench implementation, test cases development, documentation and support. Ability to work under time-scale pressure and meet ambitious targets without compromising on quality Understanding of the fundamentals of Arm system architectures Hands-on with power management protocols like Pchannel, Qchannel, etc Experience with various front-end verification tools - Dynamic simulation tools, Static Simulation tools, UPF, and Debuggers. Nice To Have Skills and Experience : Possess knowledge of object-oriented programming concepts Practical experience of working on Processor-based system design Experience in Client SOC Should have team handling experience Familiarity of Unix / Linux working environment

Support in requirement gathering from customer and defining the specification Co-ordinate with system team for deriving the system/HW architecture Support team in HFS, detailed design and development. Support development activities like PCB input and reviews, power supply design, BOM, stack up, etc Co-ordinating with cross functional team like diagnostics, SI/PI, mechanical, thermal, FPGA, RF etc Provide guidance for Board bring up, interface testing, design validation etc Support regulatory and compliance testing specification. Support for Proto/Pilot and mass production. Interaction with various vendors/ OEMs to identify more optimized solutions. Supporting quality team to adhere to standards. Qualifications: BE/B.Tech/M.E/M.Tech or its Equivalent Domain skills Strong experience in defining the HW architecture in co-ordination with system team Strong Hardware Design Capabilities for networking product design Experience in handling processor-based design, SoC, ASIC, FPGA and network related components. Experience in Handling Complete Product Design Life Cycle Good hands-on experience in High speed design like DDR5, LPDDR4, DDR4, PCIe, XAUI, RXAUI, XFI, SFI, XLAUI, SFP28, EMMC, Ethernet SGMII, RGMII, USB 3.0, eCPRI, JESD204, JTAG etc Strong debugging capabilities involving FPGA, processor, ASIC, analog and digital domain. Good command over timing solutions like syncE and 1588 . Sound and hands-on experience in Product Compliance/Regulatory standards and testing Experience in Analog, Digital, and Mixed-signal board design Experience in board bring up and supporting diagnostic team Knowledge of Schematic & PCB design tools like Cadence Hands-on experience in usage of HW tools like Oscilloscope, Signal analyzer, Network analyzer, Spectrum analyzer, etc

Digantara is a leading Space Surveillance and Intelligence company focused on ensuring orbital safety and sustainability. With expertise in space-based detection, tracking, identification, and monitoring, Digantara provides comprehensive domain awareness across regimes, allowing end users to have actionable intelligence on a single platform. At the core of its infrastructure lies a sophisticated integration of hardware and software capabilities aligned with the key principles of situational awareness: perception (data collection) , comprehension (data processing) , and prediction (analytics) . This holistic approach empowers Digantara to monitor all Resident Space Objects (RSOs) in orbit, fostering comprehensive domain awareness. Digantara seeks an FPGA design Engineer to design and develop RTL modules for satellite payload electronics. The engineer will implement image processing algorithms and suitable data, control interfaces between the payload the satellite bus. Why Us Competitive incentives, galvanizing workspace, blazing team, frequent outings pretty much everything you have heard about a startup + you get to work on space technology. Hustle in a well-funded startup allowing you to take charge of your responsibilities and create your moonshot. Ideal Candidate: Someone with expertise in FPGA design for the satellite payload electronics/ground-based imaging systems. Responsibilities: Design and develop high-performance RTL modules for the FPGA-based payload electronics, to accomplish on-board image capture and processing. Develop high quality RTL and efficient custom IP blocks in VHDL/Verilog for AMD-Xilinx/Microchip FPGA target devices. Implement high-speed interfaces with a processor such as SerDes, Gigabit ethernet, PCIe, and AXI-4/AXI-4 Lite interface. Carry out Synthesis, Place and Route, static timing analysis (STA) and close the timing requirements of the FPGA design. Collaborate with hardware, embedded software, and image processing engineers to generate RTL design requirements, architecture, and test plans. Document the FPGA design, verification and validation, board level test results throughout the development lifecycle. Required Qualifications B.Tech/B.E in Electronics Engineering or M.Tech/M.E or PhD in Microelectronics/Embedded systems/VLSI. 4 to 6 years of demonstrated experience in RTL design and development for FPGA based digital systems. Strong proficiency in VHDL/Verilog based digital logic implementation with expertise in FPGA design flow using Vivado/Libero EDA tools. Deep understanding of FPGA architecture, Synthesis and Static Timing Analysis, Clock domain crossing techniques, and timing closure. Strong expertise in troubleshooting logical and timing observations during the development lifecycle. Proficiency in working with FPGA/SoC development kits and electronic test equipment. Preferred Skills Familiarity with digital image processing and image compression implementation on FPGA. Experience in developing reliable and robust FPGA designs for satellite payloads is a significant plus. Experience with Questasim or similar tools for functional verification and code coverage analysis. Knowledge of Embedded software development in C/C++ and algorithm implementation in MATLAB/Python. Knowledge of the latest advancements in FPGA based payload electronics development. Familiarity with the standards for satellite hardware development is an advantage. General Requirements Ability to work in a mission-focused, operational environment. Ability to think critically and make independent decisions. Interpersonal skills to enable working in a diverse and dynamic team. Maintain a regular and predictable work schedule. Writing and delivering technical documents and briefings. Verbal and written communications skills as well as organizational skills. Travel occasionally as necessary. Job Location: Hebbal, Bengaluru. Work Type: WFO with alternate Saturdays.

Hardware Engineer Testing Please work on the below requirement Qualification : BE ( ECE / equivalent) Exp level : 3 to 5 yrs Notice period: 30 days Location : Cisco BLR ( Onsite only, no WFH) Budget: Upto 15 LPA Highlighted color is mandatory skill Interview mode: F2F Knowledge of System bring up based on embedded processor and Network ASICs Knowledge on Scripting and Test Log analysis Test plan preparation for system testing, and test log review Good experience in Board Bring-up, Hardware and System level debugging Good understanding of interfaces like DDR-2/3/4, PCIe, SerDes protocols Good experience on management interface like SPI, I2C Proven experience on preparation of Functional Specifications, Production Definition and taking ownership on Documentation Hands on with the usage of design tools from Mentor Graphics and Cadence Hands on with the usage of Digital Oscilloscope, Multimeters, test and measuring equipment Skills Hands on experience on lab test equipments, MSO, DSA, spectrum analyzer, counters, signal generators, AC/DC source, E-Loads, Surge generator Hands-on experience on network protocol testers Hands-on knowledge on Freescale code warrior, Xilinx tools Hands-on experience on eMMC/SATA, I2C SPI bus, PCIe analyzers P2020, TMS320DM642 DSP, Zilog controller, PIC controllers, Network processors, 8051, 89C58, Xilinx, Altera, Atmel FPGA, CPLD, EPLD based designs. CPCI, Mini PCI, PCIe, USB, Ethernet, MIL1553B, JTAG,I2C, I2S, SPI, RS232, RS422 Video and Audio interfaces, DAC, ADC, LCD SRAM, NAND, NOR Flash, DDR3 SDRAM, SD card Memory interfaces Stepper motor drive circuits, Relay control, Sensor Interface circuits, Keypad Interfaces Experience in EDA tools ORCAD Capture, Allegro, PADS PCB Design of Automated test equipment, Board test adapters. Overview Offered Salary 15LPA Experience 3-5 YEARS Qualification BE(ECE/Equivalent)