777 Fpga Jobs - Page 17

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Preferred Qualifications: Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 5+ years of Hardware Engineering or related work experience. 2+ years of experience with circuit design (e.g., digital, analog, RF). 2+ years of experience utilizing schematic capture and circuit simulation software. 2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc. 1+ year in a technical leadership role with or without direct reports. Principal Duties and Responsibilities: Leverages Hardware knowledge and experience to plan, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. Integrates features and functionality into hardware designs in line with proposals or roadmaps. Conducts complex simulations and analyses of designs as well as implements designs with the best power, performance, and area. Collaborates with teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality. Evaluates, characterizes, and develops the manufacturing solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules. Evaluates reliability of critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity. Evaluates complex design features to identify potential flaws, compatibility issues, and/or compliance issues. Writes detailed technical documentation for Hardware projects. Level of Responsibility: Works independently with minimal supervision. Provides supervision/guidance to other team members. Decision-making may affect work beyond immediate work group. Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. J Principal Responsibilities: Senior leader with 20+ CAD/Methodology development experience for team in Bengaluru. Drive tools, flows, methodologies globally as part of world-wide CAD organization. Develop and implement advanced CAD flows and methodologies for front end RTL Design to Verification Methodologies and framework development. Utilize scripting languages (python) to automate CAD/IT processes and increase efficiency. Collaborate with cross-functional teams to ensure successful integration of CAD flows. Stay up-to-date with cutting-edge technology (AI/ML), conduct thorough analysis of CAD tools and make improvements. Work closely with users to troubleshoot and resolve any issues that arise in tools, flows, environment, and infrastructure. Preferred Qualifications: Experience building full stack AI applications, with a focus on practical, production-grade solutions Strong proficiency in Rust for performance-critical systems and Python for AI development and scripting . Solid understanding of large language models (LLMs), their mechanics, and their real-world applications. Experience implementing tool use capabilities for LLMs and agent frameworks Knowledge of evaluation methodologies for fine-tuned language models Good grasp of Retrieval-Augmented Generation (RAG) and latest AI Agent frameworks Ability to stay current with the fast-evolving AI landscape]. Including advancements in LLMs and neural networks Strong understanding of CAD/EDA tools and methodologies. Hands on experience with regression systems, CI/CD, Revision Control System (git, perforce) workflow. Strong fundamentals in digital design, design verification methodologies and EDA tools. Knowledge of SOC architecture is a plus Preferred – Masters in VLSI or Computer Science Minimum – Bachelors in Electronics/Electrical Engineering/Computer Science Atleast 15 years’ experience in development of tools/flows/methodologies in either RTL, DV, synthesis, PnR or Signoff. Should have a proven record of driving new innovative tool/flow/methodology solutions. Should have managed a medium sized team. Level of Responsibility: Works independently with minimal supervision. Work with chip leads in support of design verification. Collaborate with chip leads to understand the design methodology. high-level requirements, determine other areas to support current or future designs that can benefit from automation and tooling. Provides supervision/guidance to other team members. Decision-making is significant in nature and affects work beyond immediate work group. Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. Preferred Qualifications: Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 15+ years of Hardware Engineering or related work experience. 4+ years of experience with circuit/logic design/validation (e.g., digital, analog, RF). 4+ years of experience utilizing schematic capture and circuit stimulation software. 4+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc. 4+ years in a technical leadership role with or without direct reports. Principal Duties and Responsibilities: Experience with demanding PPA requirement of complex sub-syste/SOC, place and route, IP integration. Experience in low power design Implementation including UPF, multi-voltage domains, power gating. Experience with ASIC design flows and methodology of Physical design. Understanding of circuit design, device physics and deep sub-micron technology. Should have worked on multiple TO in advance technology nodes. Person should also have good understanding of automation to drive the efforts to improve the PPA Level of Responsibility: Provides supervision to direct reports. Decision-making is critical in nature and highly impacts program, product, or project success. Requires verbal and written communication skills to convey highly complex and/or detailed information. May require strong negotiation and influence with large groups or high-level constituents. Works within the prescribed budgetary objectives of the department. Has a great degree of influence over key organizational decisions. Tasks often require multiple steps which can be performed in various orders; extensive planning, problem-solving, and prioritization must occur to complete the tasks effectively.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Excellent Design verification domain expertise. Develop test strategy, TB architecture and test plan for new IP’s/new features Develop strategies for re-useable, scalable and enhance Sub system level verification environment Excellent C/System Verilog/Verilog skills to handle C based TB environment Strong skills in debug, post silicon debug-failure re-creation and root cause analysis Scripting proficiency - PERL, Python, for developing applicable automation AMBA, AXI bus protocols Power intent verification, GLS etc. Capable of communicating effectively with all stakeholders across the globe Capable of seeding a new team for new IPs, able to hire and expand the team in expertise and efficiency Capable of mentoring the team members for their career growth, maintaining diversity in the team, collaborating with other leads and managing multiple parallel projects Take initiatives to enable various ideas for improving efficiencies. Good to have Image Processing, DSI/DP/HDMI Protocols Good knowledge of new methodologies, flows and tools to be incorporated. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Role & responsibilities Good at C/C++ language Prior knowledge to tools like Vivado/Vitis Scripting languages TCL/Python Embedded systems Understanding of Hardware like processors/SoC/FPGA/Memories/etc.. Problem solving/HW Debugging skills Linux - basic knowledge

Software Principal Engineer The Software Engineering team delivers next-generation application enhancements and new products for a changing world. Working at the cutting edge, we design and develop software for platforms, peripherals, applications and diagnostics all with the most advanced technologies, tools, software engineering methodologies and the collaboration of internal and external partners. Join us to do the best work of your career and make a profound social impact as a Software Principal Engineer on our 5G RAN FPGA Verification Team in Bangalore . What you ll achieve As a Software Principal Engineer, you will be responsible for developing sophisticated systems and software based on the customer s business goals, needs and general business environment creating software solutions. You will: Contribute to the design and architecture of high-quality, complex systems and software/storage environments Prepare, review and evaluate software/storage specifications for products and systems Contribute to the development and implementation of test strategies for complex software products and systems/for storage products and systems Take the first step towards your dream career Every Dell Technologies team member brings something unique to the table. Here s what we are looking for with this role: Essential Requirements Experience in FPGA systems design and verification with Verilog coding, System Verilog, and VHDL coding practices. Experience in UVM Verification framework, Assertion based Verification, Code coverage, Unit level simulations. Experience in E2E bench setup and HW validation. Very strong debugging skills Experience in RTL Design Digital Design Principles and peripheral protocol. Strong fundamentals in both analog and digital design practices with a desire to share knowledge and mentor others Experience and deep knowledge of hardware and software interactions, and ability to apply this understanding to resolve issues. Desirable Requirements 8-12 years of relevant experience or equivalent combination of education and work experience Experience in MATLAB and Simulink modelling for 5G flow Application closing date: 20 July 2025

Senior Software Engineer The Software Engineering team delivers next-generation application enhancements and new products for a changing world. Working at the cutting edge, we design and develop software for platforms, peripherals, applications and diagnostics all with the most advanced technologies, tools, software engineering methodologies and the collaboration of internal and external partners. Join us to do the best work of your career and make a profound social impact as a Senior Software Engineer in our 5G RAN FPGA Team in Bangalore What you ll achieve As a Senior Software Engineer, you will be responsible for developing sophisticated systems and software basis the customer s business goals, needs and general business environment creating software solutions. You will: Contribute to the design and architecture of new or re-engineered software/storage environments Prepare written software/storage specifications for sophisticated products from architectural diagrams and documents Build and review design, functional, technical and/or user documentation, as needed Develop, review and implement test strategies for software products and systems Take the first step towards your dream career Every Dell Technologies team member brings something unique to the table. Here s what we are looking for with this role: Essential Requirements Expert in MATLAB and Simulink modelling for 5G flow Expert in designing, implementing, and testing new blocks for FPGA Radio platforms Expertise in NR/LTE/eCPRI/CPRI/PTP protocol analysis and implementation with signal processing knowledge and background 5G Radio development background Good in Python and scripting languages Desirable Requirements 5-8 years of relevant experience or equivalent combination of education and work experience Application closing date: 20 July 2025

Embedded Software Engineer - RTOS & Post-Silicon Validation About the Role Join the RISC-V Revolution! We are looking for talented Embedded Software Engineers to join our Automotive MCU Platform Team, with a focus on RTOS-based Software Development and Application Verification & Validation (AVV). You will be part of a growing team building MIPS RISC-V-based real-time processors and their associated software stack - shaping the future of embedded control systems for automotive applications like EVs, ADAS, powertrain, and domain controllers. This is a unique opportunity to contribute across the full silicon-to-software lifecycle, combining software engineering with post-silicon validation to ensure high-quality, safety-critical SoC solutions. What We Offer At MIPS, you ll be a member of a fast-growing team of technologists that are creating the industry s highest performance RISC-V processors. Small teams that are part of a non-compartmentalized structure - you ll be able to understand and have an impact on the bigger picture. A great deal of autonomy, with support from some of the industry s most experienced CPU engineers. An unlimited growth path - with the right skills, you can decide where you want to expand and grow in your role at MIPS. The opportunity to learn a great deal about the blossoming RISC-V architecture in cutting-edge applications with industry-leading customers. Responsibilities Develop embedded software components for RTOS-based SDKs, including Low-Level Drivers (LLDs), HALs, RTOS abstraction layers, and BSPs. Develop example, demo applications to showcase peripheral functionality and performance. Support post-silicon validation (AVV) by creating validation test apps that reuse RTOS SDK components. Bring up first silicon and validate critical peripherals (ADC, PWM, CAN, LIN, watchdogs, etc.). Support automation of lab and CI-based test execution. Collaborate across teams - work closely with architecture, hardware, safety, and tools teams to align software with silicon capabilities and roadmap. Contribute to reference software and tooling to aid customers in bootstrapping their own designs. Analyze and debug complex issues using emulators, silicon, and debug tools like OpenOCD, J-Link, or Lauterbach. Provide feedback into next-gen MCU architecture, based on software validation findings. Contribute to the wider RISC-V software ecosystem, helping to ensure support for the architecture in various open-source projects. Qualifications 3-8 years of hands-on experience in embedded systems software development. Strong skills in C, C++ programming, with basic familiarity in assembly. Good understanding of RTOS concepts (task scheduling, ISRs, semaphores, etc.). Experience debugging complex multicore systems, experience with debugging tools (OpenOCD, Segger J-Link, Lauterbach). Experience porting or developing on FreeRTOS, Zephyr, AUTOSAR OS, or similar platforms. Familiarity with bare-metal development, memory-mapped IO, and driver development. Experience in bring-up and debugging on real silicon or FPGA platforms. Knowledge of automotive interfaces and protocols CAN, LIN, SPI, I2C, UART. Practical exposure to test automation, scripting (Python, bash), and version control (git). Bonus Points Exposure to ASIL-D software development, ISO 26262 process, or safety validation. Prior involvement in post-silicon AVV or hardware-in-the-loop (HIL) test setups. Familiarity with RISC-V architecture, instruction sets, and toolchains. Experience developing or validating motor control, powertrain, or safety-critical firmware. Knowledge of bootloaders, secure update, or system startup firmware. Benefits Opportunity to work on cutting-edge RISC-V platforms with real industry adoption. A fast-paced, engineering-driven environment with minimal red tape. Mentorship from veteran CPU and embedded software engineers. Direct involvement in building safety-critical systems from the ground up. Exposure to a full-stack SoC development lifecycle from pre-silicon to production-ready. Flexible growth path - whether you want to specialize deeply or lead in the future. About MIPS MIPS is well-known as a microprocessor pioneer, having led the way in RISC-based computing to enable faster and more power-efficient semiconductors for a wide range of applications from consumer electronics to networking and communications. More than 30 years after the introduction of the original MIPS RISC architecture, MIPS processors have shipped into billions of consumer and enterprise products. Today, MIPS is once again leading a RISC revolution as we build on our deep roots to accelerate the RISC-V architecture for high-performance applications. We are focused on delivering our first RISC-V products - the MIPS eVocore processors, which provide a new level of scalability for high-performance heterogeneous computing. Because of our RISC heritage, deep engineering expertise, and proven technologies, MIPS can accelerate development and deployment of RISC-V-based solutions.

Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Data Center Networking Technologies Operations Good to have skills : Infoblox DNS/ BloxOne &, Infoblox DDIMinimum 5 year(s) of experience is required Educational Qualification : 15 years full time educationhighly skilled Network Engineer with extensive experience in Infoblox DNS, specifically BloxOne & NIOS, to join our dynamic team. This role will be instrumental in ensuring the reliability, security, and optimal performance of our organization's critical network infrastructure.Responsibilities:DNS Administration:Manage and maintain Infoblox NIOS appliances, including configuration, troubleshooting, and performance tuning.Implement and enforce DNS security best practices, such as DNSSEC, DNS Firewall, and IP Threat Defense.Design and implement DNS failover and redundancy strategies to ensure high availability.Troubleshoot DNS-related issues, including DNS resolution failures, slow DNS queries, and DNS attacks.IP Address Management (IPAM):Manage and allocate IP addresses using Infoblox IPAM.Monitor IP address utilization and plan for future growth.Implement IP address management policies and procedures.DHCP:Configure and manage DHCP services using Infoblox DHCP.Troubleshoot DHCP-related issues, such as IP address conflicts and DHCP lease failures.Network Automation:Automate routine tasks using scripting languages (e.g., Python, PowerShell) and APIs to improve efficiency and reduce human error.Develop and maintain automation scripts for DNS, DHCP, and IPAM tasks.Security:Stay up-to-date with the latest security threats and vulnerabilities related to DNS and IPAM.Implement security measures to protect the network infrastructure from attacks.Conduct regular security audits and vulnerability assessments.Troubleshooting:Diagnose and resolve complex network issues, including DNS, DHCP, and IPAM problems.Utilize network troubleshooting tools to identify and isolate network failures.Documentation:Create and maintain clear and concise documentation for network configurations, procedures, and troubleshooting steps. Qualifications:Strong understanding of DNS, DHCP, and IPAM protocols.Extensive experience with Infoblox NIOS, including BloxOne DDI.Proficiency in scripting languages (e.g., Python, PowerShell).Knowledge of network security best practices.Strong troubleshooting and problem-solving skills.Excellent communication and interpersonal skills.Ability to work independently and as part of a team.Relevant certifications (e.g. CCNA, CCNP, DDIA, DDIP ) are preferred.If you are a passionate network engineer with a strong foundation in Infoblox DNS and a desire to work on cutting-edge technologies, we encourage you to apply. Qualification 15 years full time education

Greetings from Tamilnadu Advanced Technical Training Institute (TATTI)! We are looking for an experienced Verilog and VHDL Trainer to deliver practical and conceptual training in digital system design. The role involves guiding learners through hands-on sessions using industry-relevant tools, preparing them for roles in the semiconductor and embedded systems domain. Job Type: Freelance Location: Chennai Key Responsibilities: Conduct training sessions on Verilog and VHDL Develop course materials, lab exercises, and projects Mentor learners and support project development Stay updated with trends in FPGA, ASIC design, and EDA tools Requirements: Proficiency in Verilog and VHDL Experience with tools like ModelSim, Vivado, Quartus etc. Strong communication and presentation skills Prior teaching/training experience is a plus Why Join TATTI Work with a renowned technical training institute with over 40 years of experience . Collaborate with leading corporate clients . Enjoy career growth and continuous learning opportunities. Be part of an innovative and dynamic team . Apply Now: Interested, Click the link to apply!

Role & responsibilities FPGA, RTL, DO-254,VHDL, VERILOG, XILINX, LIBERO, AVIONICSJ Preferred candidate profile

Project Role : Application Developer Project Role Description : Design, build and configure applications to meet business process and application requirements. Must have skills : SAP Sales and Distribution (SD) Good to have skills : Pricing Analytics and ModellingMinimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Developer, you will design, build, and configure applications to meet business process and application requirements. Your day will involve collaborating with teams to develop solutions and ensure seamless application functionality. Roles & Responsibilities:-Responsible for analyzing business/technical needs and translating process into practice through the current Information Technology tool sets. The role will also implement new solutions through configuration and creation of functional specifications and facilitate solution realization. In addition, the role will have responsbilities for conducting testing and trouble shooting solutions.- Analyze business/technical needs and translate process into practice through the current Information Technology tool sets.- Implement new solutions through configuration and creation of functional specifications and facilitate solution realization.- Conduct full integration testing of new or changed business/technical processes. Develop business/technical cycle tests for use by stakeholder community. Document all process changes and provide knowledge to relevant stakeholders- Troubleshoot, investigate and persist. Develop solutions to problems with unknown causes where precedents do not exist by applying logic and inference with creativity and initiative. Provide cross-functional support and maintenance for responsible business/technical areas.- Conduct cost/benefit analysis through evaluation of alternative design approaches to determine best-balanced solution. Best-balanced solution is one that satisfies the immediate stakeholder needs, meets system requirements and facilitates subsequent change.- Assume leadership role in a small size initiatives by playing the key contributor, facilitator or group lead. Professional & Technical Skills: - Must To Have Skills: Proficiency in SAP Sales and Distribution (SD)- Good To Have Skills: Experience with Pricing Analytics and Modelling- Strong understanding of SAP SD modules and functionalities- Experience in customizing and configuring SAP SD applications- Knowledge of integration with other SAP modules- Ability to troubleshoot and resolve technical issues efficiently Additional Information:- The candidate should have a minimum of 5 years of experience in SAP Sales and Distribution (SD)- This position is based at our Hyderabad office- A 15 years full-time education is required Qualification 15 years full time education

Performance Benchmarking Lead Job Description We are seeking an experienced engineer to lead Performance Benchmarking of RISC-V CPUs. This position requires a candidate with knowledge and interest in performance benchmarking, computer architecture, and experience working on pre- and post-silicon platforms. The candidate will contribute to the advancement of MIPS high-performance designs through their benchmarking and analysis work, as part of the MIPS Performance and Architecture team. Responsibilities Provide Technical Leadership to a team of Performance Benchmarking engineers. Create and maintain the infrastructure to carry out benchmarking on RTL Simulation, FPGA and Silicon. Carry out Competitive Analysis and Research industry trends. Analyze and debug performance issues. Work closely with Product and Design teams to help improve performance of MIPS products. Ideal Candidate Profile Strong Background in Performance Benchmarking and CPU Microarchitecture. Familiarity with industry standard benchmarks including SPEC, Lat-mem, Stream. Background in programming - C, Python. Hands-on experience working with FPGAs, Boards, Linux. Hands-on experience setting up and improving automation frameworks. Prior experience in leading teams. Plus Familiarity with microarchitecture constructs - for e.g. TLBs and caches. Experience with RISC-V and,or MIPS CPU architecture. Linux Kernel experience. Compiler toolchain experience.

Job Description. Arm’s CE-Systems DFT team implements DFT for test chips and hard macros to prove out Arm soft IP power, performance, area, and functionality within the context of an SoC using the latest DFT and process technologies. The DFT team works closely with RTL, Verification, Physical Implementation, and Test engineering teams throughout the life cycle of a project, from an early investigation stage all the way through tape-out and silicon test/characterization on ATE.. Responsibilities. Architect, implement, and validate innovative DFT techniques on test chips as well as hard macros. Insert DFT logic into SoC style designs at the RTL level and at the Synthesis gate level, validate all features, and generate ATE targeted test patterns to be run on silicon. Work closely with front-end design and verification teams on DFT RTL level insertion, back-end synthesis, place-and-route, and static-timing-analysis teams on gate level insertion and timing closure, and Test and Debug teams on silicon characterization and validation.. Required Skills And Experience. This role is for a Senior Principal DFT Engineer with 15+ years of experience in Design for Test. Experience coding Verilog RTL, TCL and/or Perl. Proficient in Unix/Linux environments. Core DFT skills considered for this position should include some of the following Scan compression and insertion, Memory BIST and repair scheme implementation, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate level verification, silicon debug, memory and scan diagnostics. Bachelors or Master’s degree or equivalent experience in Electronic Engineering, Computer Engineering, or a related field. “Nice To Have” Skills and Experience. Familiarity with IEEE 1149, 1500, 1687, 1838. Synthesis & Static Timing Analysis. Familiarity with SoC style architectures including multi-clock domain and low power design practices.. Validated understanding of Siemens DFT tools. Familiarity with Arm IP like the following Cortex CPUs, Mali GPUs, AMBA protocols, CoreLink interconnects, CoreSight debug. Experience with 2.5D and 3D test. Ability to work both collaboratively on a team and independently. Hard-working and excellent time management skills with an ability to multi-task. An upbeat demeanor to working on exciting projects on the cutting edge of technology. Experience with Siemens, Cadence, and/or Synopsys DFT and simulation tools. In Return. We are proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work together to defy ordinary and shape outstanding!. Partner and customer focus. Teamwork and communication. Creativity and innovation. Team and personal development. Impact and influence. Deliver on your promises. Accommodations at Arm. At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.. Hybrid Working at Arm. Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.. Equal Opportunities at Arm. Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.. Show more Show less

In your new role you will:. Manage a Digital Verification Team working in R&D projects in a complex technical area. Resource pipeline balancing, allocate projects and co-ordinate the team. Building up and developing competencies and methodologies for IP/SoC Verification. Be the technical interface to internal development groups, project management and external development partners. Drive innovation in the form of new advancements (state-of-the-art verification methods, tool integration and flow automation). Envisage, implement, institutionalize and maintain the verification methods and infrastructure (e-g. automation to improve quality/efficiency in terms of cost and time). Accountable together with the PJM & CoC Head in meeting Quality, Cost, Deliverables, Represent your group in cross site methodology exchange. You are best equipped for this task if you have:. A degree in Electrical Engineering, Computer Science or similar technical field. At least 10 years of experience in the semiconductor industry inrelevant R&D departments and people management experience is must. Experience in Product Development, Digital Verification or Digital Design. Profound and proven problem-solving capabilities as well as strong communication skills to manage global and multi-cultural stakeholders and networks successfully. Good knowledge in your own technical area but a focus on management and coordination role. Excellent presentation skills which enable you to master the alignment across internal and external contacts in a multi-cultural environment. Highly motivated with ability to prioritize and perform under pressure. Proven ability to achieve results in a very dynamic and multi-site environment. Strong analytical and communication skills. #WeAreIn for driving decarbonization and digitalization, As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener, Are you in?. We are on a journey to create the best Infineon for everyone, This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicants experience and skills, Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process, Click here for more information about Diversity & Inclusion at Infineon, Show more Show less

WHAT YOU DO AT AMD CHANGES EVERYTHING. We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.. AMD together we advance_. PMTS SOFTWARE DEVELOPMENT ENGINEER. The Role. AMD is looking for a strategic software engineering lead who has a passion for enhancing User Interface, specifically for FPGA Software. This role is truly a unique chance to join a core team composed of incredibly talented industry specialists and work with the latest UI technologies. The Person. The ideal candidate should be passionate about software engineering and possess leadership skills to drive sophisticated issues to resolution. Able to communicate effectively and work optimally with different teams across AMD. A good understanding of FPGA is beneficial.. Key Responsibilities. Work with AMD’s architecture specialists to improve future products. Apply a data minded approach to target optimization efforts. Stay informed of software and hardware trends and innovations, especially pertaining to UI and architecture. Design and develop new groundbreaking AMD technologies. Debugging/fix existing issues and research alternative, more efficient ways to accomplish the same work. Develop technical relationships with peers and partners. Preferred Experience. Strong experience in developing extensions for VS Code or similar IDEs preferred. E/B. Proficiency in JavaScript/TypeScript, React, and WebView for building modern web-based user interfaces in desktop applications. Strong experience working with Java-based backend systems and integration using gRPC for high-performance communication. Hands-on experience with gRPC, including defining services, creating clients and servers, and troubleshooting communication issues. Ability to write high quality code with a keen attention to detail. Experience with modern concurrent programming and threading APIs. Experience with Windows, Linux and/or Android operating system development. Experience with software development processes and tools such as debuggers, source code control systems (GitHub) and profilers is a plus. Effective communication and problem-solving skills. Motivating leader with good interpersonal skills. Academic Credentials. Bachelor’s or Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent. Benefits offered are described: AMD benefits at a glance.. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.. Show more Show less

Minimum qualifications:. Bachelor’s degree in Electrical Engineering or Computer Engineering, or equivalent practical experience.. 15 years of experience in ASIC RTL design.. Experience with RTL design using Verilog/System Verilog and microarchitecture.. Experience with ARM-based SoCs, interconnects and ASIC methodology.. Preferred qualifications:. Master’s degree in Electrical Engineering or Computer Engineering.. Experience driving multi-generational roadmap for IP development.. Experience leading interconnect IP design team for low power SoCs.. About The Job. Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.. Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.. Responsibilities. Lead a team of people to deliver fabric interconnect design.. Develop and refine RTL design to aim power, performance, area, and timing goals.. Define details such as interface protocol, block diagram, data flow, pipelines, etc.. Oversee RTL development, debug functional/performance simulations.. Communicate and work with multi-disciplined and multi-site teams.. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .. Show more Show less

Minimum qualifications:. Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.. 5 years of experience in High Bandwidth Memory/Double Data Rate (HBM/DDR).. Experience in silicon bringup, functional validation, characterizing, and qualification.. Experience with board schematics, layout, and debug methodologies with using lab equipment.. Preferred qualifications:. Experience in hardware emulation with hardware/software integration.. Experience in coding (e.g., Python) for automation development.. Experience in Register-Transfer Level (RTL) design, verification or emulation.. Knowledge of SoC architecture including boot flows.. Knowledge of HBM/DDR standards.. About the jobIn this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.. In this role, you will be responsible for post-silicon validation of the Cloud Tensor Processing Unit (TPU) projects. You will create test plans and test content for exercising the various subsystems in the Artificial Intelligence/Machine Learning (AI/ML) System on a Chip (SoC), verify the content on pre-silicon platforms, execute the tests on post-silicon platforms, and triage and debug issues. You will work with engineers from architecture, design, design verification, and software/firmware teams. You will be validating the functional, power, performance, and electrical characteristics of the Cloud Tensor Processing Unit (TPU) silicon to help deliver high-quality designs for next generation data center accelerators.The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.. We prioritize security, efficiency, and reliability across everything we do from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.. Responsibilities. Develop and execute tests for memory controller High Bandwidth Memory (HBM) post-silicon validation and on hardware emulators and assist in bring-up processes from prototyping through post-silicon validation.. Drive debugging and investigation efforts to root-cause, cross-functional issues. This includes pre-silicon prototyping platforms as well as post-silicon bringup and production.. Ensure validation provides necessary functional coverage for skilled design.. Help operate and maintain our hardware emulation platform for pre-silicon integration and validation.. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .. Show more Show less

Job Description. As an FPGA Engineer specialised in RTL (Register Transfer Level) coding, you will be responsible for designing, optimising, and implementing hardware solutions on Field-Programmable Gate Arrays (FPGAs) to support high-frequency trading strategies. You will work closely with the trading systems team to develop and deploy ultra-low latency trading infrastructure, ensuring the highest levels of performance, reliability, and efficiency.. Key Responsibilities. RTL Design and Optimisation: Design and optimise FPGA-based solutions using RTL coding techniques to achieve ultra-low latency and high throughput for trading algorithms and strategies.. Algorithm Implementation: Implement trading algorithms and strategies in hardware, leveraging FPGA capabilities to minimise latency and maximise performance.. Hardware Acceleration: Identify opportunities for hardware acceleration of critical trading functions and develop FPGA-based solutions to achieve significant speedups.. Performance Analysis and Tuning: Conduct performance analysis of FPGA designs, identify bottlenecks, and fine-tune the implementations to achieve optimal performance.. Hardware Integration: Collaborate with software engineers and system architects to integrate FPGA-based solutions into the overall trading infrastructure, ensuring seamless operation and compatibility.. Testing and Validation: Develop test benches and perform thorough testing and validation of FPGA designs to ensure correctness, reliability, and robustness under real-world trading conditions.. Documentation and Reporting: Document FPGA designs, methodologies, and implementation details, and provide regular reports and updates to stakeholders on project progress and performance metrics.. Requirements. Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.. Proven experience in FPGA design and development, with a focus on RTL coding using Verilog or VHDL.. Deep understanding of computer architecture, digital design principles, and hardware/software co-design concepts. Experience with high-frequency trading systems and ultra-low latency design techniques is highly desirable.. Proficiency in FPGA development tools and workflows, such as Xilinx Vivado or Intel Quartus.. Strong analytical and problem-solving skills, with the ability to optimise designs for performance, power, and resource utilisation.. Excellent communication and collaboration skills, with the ability to work effectively in a fast-paced, team-oriented environment.. Show more Show less

WHAT YOU DO AT AMD CHANGES EVERYTHING. We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.. AMD together we advance_. PMTS SILICON DESIGN ENGINEER. As a SerDes Verification Architect, you will be responsible for the verification and validation of high-speed SerDes interfaces, including testing data integrity, performance, and protocol compliance. You will work closely with hardware and design teams to ensure that SerDes designs meet the required specifications, operating parameters, and quality standards.. Key Responsibilities. Verification of SerDes Designs: Develop and execute verification plans and testbenches for SerDes IPs (Intellectual Property) and subsystems to ensure they meet functional and performance requirements.. Testbench Development: Design and implement verification testbenches using industry-standard verification methodologies (e.g., UVM, SystemVerilog, VHDL).. Simulation and Debugging: Perform simulations, analyze results, and debug issues related to timing, protocol errors, and other design anomalies in SerDes blocks.. Performance Evaluation: Evaluate and validate performance characteristics of SerDes systems including jitter, bit error rates (BER), signal integrity, eye diagrams, and other key metrics.. Protocol Compliance Testing: Verify adherence to relevant SerDes protocols such as UCIe, PCIe, Ethernet, USB, DDR, DisplayPort, or custom protocols.. Automated Testing: Develop automated regression tests to ensure the robustness and stability of the SerDes design over multiple versions and iterations.. Collaboration: Work closely with the design, hardware, and software teams to troubleshoot issues, implement fixes, and verify design changes.. Documentation: Create detailed reports and documentation on verification results, test scenarios, and issues found during testing.. Verification methodology: Provide feedback for design and verification process improvements and contribute to innovation in verification strategies and methodologies.. Experience:. 16+ years of experience in SerDes verification or high-speed communication verification.. Strong hands-on experience with verification methodologies such as UVM, SystemVerilog, or other simulation-based verification tools.. Knowledge of high-speed serial protocols such as UCIe, PCIe, Ethernet, USB, DDR, or custom protocols.. Experience in analyzing and interpreting signal integrity issues, jitter, BER, and eye diagrams.. Skills:. Solid understanding of SerDes architectures, link training, and equalization.. Strong debugging skills, with the ability to work across multiple domains (timing, protocol, performance).. Familiarity with hardware description languages (HDL) like VHDL or Verilog.. Strong analytical, problem-solving, and communication skills.. Experience with DDR protocol (e.g., DDR3, DDR4, DDR5) for memory interface verification.. Understanding of UCIe protocol and its role in chiplet-to-chiplet communication.. Preferred Skills. Experience with Python, Perl, or similar scripting languages for automation.. Exposure to high-speed memory interface design and verification, including DDR controller IP verification.. Functional coverage, assertions knowledge in SV/UVM.. Ability to work in a fast-paced environment and manage multiple verification tasks.. Strong team player with good interpersonal and communication skills.. Benefits offered are described: AMD benefits at a glance.. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.. Show more Show less

Our solutions are a key part of most industries - electronics, medical research, renewable energy, food production, infrastructure and many more. Working with us means working with the latest technologies and groundbreaking, sustainable innovations. Join us on our journey for a better tomorrow. Your Role Atlas Copco is a leading global Industrial Group having vision of "First in Mind, First in Choice". Our culture is founded on three core values of commitment, interaction and innovation. They guide us in everything we do and reflect how we behave internally and in our relationships with our stakeholders. Digital Technology Practice at GECIA (Global Engineering Centre, India), part of Atlas Copco, is contributing significantly to vision of the Group by focusing on developing global talent, expanding portfolio and competence on futuristic competencies, driving Innovation and achieving operational excellence to drive customer success. As an Embedded Systems Engineer, your mission will be to bring in strong knowledge skills and ability to absorb knowledge and develop applications in electronics and instrumentation. Together with our team, you will not only work on our advanced control systems and algorithm but also on our next generation platform of controllers. We expect you to have a strong interest in Embedded Systems Hardware and Control systems development. You will be working on design and development of various products boards. You will be part of the team which is responsible for various activities like, component selection , hardware design, PCB design, prototype etc. You will be working with various compliances like Reach and RoHS. To succeed, you will need Degree in Industrial Electronics / Electronics & Telecommunication with 8+ years industrial working experience. Knowledge of microprocessor, FPGA and memory circuits, power supply design. Experience on working with Analog, Mixed Signal, High Speed designs is a must. Knowledge of circuit simulation, signal integrity, EMI/EMC standards. Experience in design and development integrate microcontroller unit (MCU) peripheral circuits. Experience in developing turn-key power supply electronic designs, including high-efficiency AC/DC and DC/DC converters. Knowledge of pulse-width modulation (PWM) techniques and motor drive circuits. Good knowledge on isolation standards and techniques Experience in selection of power components such as discrete PWM controllers, PMMIC, high and low side driver, IGBT, MOSFET, SCR, diodes, capacitor, and inductors. Japanese language expertise is a plus. In return, we offer you An opportunity to work with 150 years old, leading global product company An opportunity where you are empowered to drive your own professional journey A challenging role focused on Technology and Innovation Global exposure and opportunities through internal mobility Freedom and authority to act A culture where we care about each other and world around us Best in class total reward program covering Insurances, Higher Education, flexible work timing

We are seeking a dynamic and visionary Software Head for Radar and Electronic Warfare (EW) systems to lead the architecture, development, and integration of mission-critical software for surveillance, electronic support (ES), and electronic attack (EA) platforms. The ideal candidate will possess a strong background in embedded systems, radar signal processing, jamming algorithms, and tactical software architectures for defence-grade systems. Key Responsibilities Technical Leadership Lead the full lifecycle of software development for Radar and EW subsystems: from concept, design, and development to integration and validation. Define system and software architecture for embedded radar processing, EW threat detection, tracking, classification, and jamming control. Oversee the implementation of real-time software stacks, RTOS/Linux-based systems, and hardware abstraction layers (HAL). Guide algorithmic development for: Radar signal/data processing (FFT, pulse compression, CFAR, Doppler) Kalman filters, beamforming, monopulse logic Emitter detection/classification, deinterleaving, and DRFM-based jamming Program & Team Management Build and lead a high-performing cross-disciplinary software team (embedded, DSP, algorithm, UI/UX). Drive Agile/iterative development cycles, version control (Git, SVN), and CI/CD pipelines for defence projects. Ensure timely delivery of milestone-based deliverables in line with DRDO, PSU, or services expectations. Compliance, Integration & Quality Oversee compliance with DO-178C, MIL-STD-498, ISO/IEC 12207, and cybersecurity frameworks. Collaborate with FPGA, RF, mechanical, and systems engineering leads for full-stack integration. Manage technical documentation: SDDs, ICDs, TRDs, test plans, qualification reports. Innovation & Strategy Identify opportunities to integrate AI/ML, sensor fusion, LPI/LPR techniques, and adaptive jamming into radar/EW systems. Engage with strategic partners, DRDO labs (e.g., DLRL, LRDE), and defence services to align roadmaps with national capability development. Required Qualifications B.E./B.Tech and preferably M.E./M.Tech in Electronics, Electrical, Computer Science, or a related discipline. 12-20+ years of experience in real-time embedded software development for radar and/or EW systems. Proven leadership in large-scale software projects involving DSP, signal processing, and mission software. Expertise in C/C++, Python, MATLAB, RTOS (VxWorks, QNX, Linux), and real-time optimization. Solid grasp of radar/EW principles: PRF, pulse descriptors, ECM/ECCM, jamming techniques, RF propagation, DRFM, etc. Preferred Skills and Attributes Experience with system-level integration of radar/EW systems on airborne, naval, or ground platforms. Knowledge of middleware frameworks, network protocols, tactical data links, and multi-sensor fusion. Familiarity with OpenCV, GPU programming, or CUDA for radar image processing and EW visualization. Strong documentation, presentation, and stakeholder management skills. Prior involvement in defence certification processes and DGQA/RCMA clearances. Embedded, Rtos, Software Architecture, Radar

A minimum of 3-6 years of experience in Device Driver software testing which includes a good know how of standard software development Life Cycle Experience in AUTOSAR MCAL and exposure to ISO26262 Embedded system software development or Validation using C, assembly languages Experience in the usage of NI, FPGA, oscilloscopes, logic analysers, power benches etc Experience in Embedded System Development tools such as compilers, debuggers (PLS, Lauterbach), static analysers etc Working experience in scripting languages such as Perl, python etc Experience in the development/maintenance of the test automation and continuous integration frameworks Good knowledge of computer architecture (16/32bit), real-time systems Working experience on multicore platforms Ability and willingness to work with multi-disciplinary teams Ability to perform tasks independently Autosar, Device Driver Testing, Iso26262, Mcal

We are looking for application engineer with 7+years of experience with extensive knowledge of AC/DC and DC/DC system level designs, Job Description In your new role you will: Contributing to major product cross-functional teams for both product development and customer supporting, Prototyping and producing requirements definitions for new application and solutions, Producing content in support of new GaN and controller/ gate drivers products, including: New product definition/ validation Hardware &System-level designs/ reviews including schematic, layout and componentselection for demo boards/ EVBs/ reference designs/customer requests, Deep analysis on products and find the value propositions, Technical documentation and promoting materials such as datasheets,technical reference manuals, application notes and knowledge basearticles, Technical training for external customers and Infineon Sales,Marketing and Applications Enabling customer design-in of products andsolutions through architectural collaboration, technical support,training and failure analysis, Your Profile You are best equipped for this task if you have: Bachelors/Master's degree above in Electrical Engineering or anequivalent field, Experience on Charger/ Adapters, SMPS, AC/DC, Solar, ESS, inverter,Motor Drivers is preferred Extensive knowledge of AC/DC and DC/DC system level designs with experience in testing, debugging and device selection; Strong understanding of one or more of the following category Non isolated and isolated DC/DC topologies like buck, boost, halfbridge, full bridge, multiphase converters SMPS topologies like PFC, LLC, etc Motor driver, Inverters; Solar, Energy Storage, and Industrial Power Applications, Experience with product, system or application development in asemiconductor environment Problem solver, and happy to help on customers technicalrequirements; Be familiar with software tools such as Altium Designers,Mathcad/Matlab, PLECS, Simplis/Simetrix, Labview; Familiar with digital control with FPGA or MCU/ DSP will be a plus; Understanding the switching power component MOSFET, IGBT etc GaN andSiC MOSFET experience is a plus; Teamwork, self-discipline/ motivated/ innovative and aggressive;Good verbal and written communication skills Contact: Shavin shashidhar@infineon, #WeAreIn for driving decarbonization and digitalization, As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals Be a part of making life easier, safer and greener, Are you in We are on a journey to create the best Infineon for everyone, This means we embrace diversity and inclusion and welcome everyone for who they are At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities We base our recruiting decisions on the applicants experience and skills, Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process, Click here for more information about Diversity & Inclusion at Infineon,

FPGA Design Intern at PierSight | Jobs at PierSight As per industry standards December 15th, 2024 Role: FPGA Design Intern Industry Type: Space Technology Location: Ahmedabad Employment Type: Internship (6 months) Job Description: Are you ready to join the pioneering team at PierSight Space as a FPGA Design InternWere a Space-Tech company with teams in Ahmedabad, California and Bangalore on a mission to build the worlds largest constellation of Synthetic Aperture Radar and AIS satellites for comprehensive ocean surveillance. With backing from prestigious institutional investors like Alphawave Global, Elevation Capital, All in Capital, and Techstars, were set to make a significant impact. Key Responsibilities: 0-1 years of hands-on experience in implementing designs on FPGA Strong expertise in RTL coding of complex designs using VHDL/Verilog/SV Knowledge in all aspects of FPGA design; constraint definition, synthesis, floor planning, P&R, Timing closure Create well written block level design documentation Write testbench and sequences in SystemVerilog Familiarity with lab equipment Familiarity with interface protocols Knowledge of latest FPGA architectures Exposure to scripting languages Preferred Experience: Hands on experience with FPGA design suite Libero Tcl/perl/python scripting languages Good hardware and software debugging skills Knowledge on running quality checks such as CDC Knowledge on synthesis, static timing analysis concepts Knowledge on FPGA Hardware design is added advantage Benefits: Exposure to real-world projects and hands-on experience in Space technology Mentorship from experienced engineers in the field