ISSP FPGA prototyping delivers Intel's core products, therefore you will have a unique opportunity to take part in major activities that affect the entire organization and the high-tech world.Our FPGA design verification team is in charge of validating infrastructure designs used to prototype cutting edge Intel client, devices and data centers chips.We are looking for great, highly motivated problem-solvers seeking to make significant contributions and impact on the projects they work on.In your role you will plan, design and execute scalable and robust verification environments, learn complex digital computers flows and simulate the behavior of the RTL design in purpose of debug and development using advanced verification methodologies. Qualifications Studying towards a B.Sc. or MSc in Computer Science / Electrical Engineering / Computers Engineeringsome experience with OOP (C++, Java...)some understanding of chip design frontend flow (design/validation/synthesis)any relevant chip design / verification experience is a big advantage

What Youll Be Doing: Provide advanced engineering design service and support to regional engineering team on embedded hardware including processors, FPGA and software design support. Collaborate with customers to develop, test, and debug firmware, assist with code creation, driver development on MCUs based on ARM Cortex, RISC-V, and proprietary cores. Assist customers to configure and customize embedded Linux systems, including kernel configuration, device drivers, middleware integration, and real-time patches. Design technical demonstrations, including Proof of Concepts (PoC), showcasing microcontroller/microprocessor, FPGA capabilities in real-world applications. Create high-quality documentation, including technical guides, application notes, and training materials, for internal and external use. Share technical expertise by delivering training sessions and workshops for internal engineers and customers. Attend technical and sales training in efforts to stay abreast of current technology. Develop product performance specifications and product development roadmaps Ensure accurate documentation of engineering designs and solutions for future reference. What We Are Looking For: Bachelors Degree or higher in Electronics/Electrical Engineering, Computer Science, or a related engineering field. Minimum 7 years of experience in electronics, semiconductors, embedded processors, and FPGA design. Proven experience in firmware development across multiple microcontroller platforms based on ARM Cortex, RISC-V, and proprietary cores. Advanced proficiency in C/C++ for embedded systems; familiarity with Python. Experience with kernel debugging, device tree customization, and interfacing hardware peripherals through custom drivers. Proficiency in VHDL and Verilog; knowledge of System Verilog or High-Level Synthesis (HLS) is a plus. Hands-on experience deploying machine learning models on MPUs using tools like TensorFlow Lite, OpenCV, or ONNX Runtime. Excellent problem-solving skills and a proactive approach to technical challenges. Strong communication and teamwork skills to work effectively with customers and internal teams. Passion for innovation and commitment to delivering high-quality engineering solutions. What’s In It For You: Training and professional development Performance coaching Work with fun team in a supportive environment. Work at a strong and growing company Community involvement opportunities About Arrow Arrow Electronics, Inc. (NYSE: ARW), an award-winning Fortune 133 and one of Fortune Magazine’s Most Admired Companies. Arrow guides innovation forward for over 220,000 leading technology manufacturers and service providers. With 2023 sales of USD $33.11 billion, Arrow develops technology solutions that improve business and daily life. Our broad portfolio that spans the entire technology landscape helps customers create, make, and manage forward-thinking products that make the benefits of technology accessible to as many people as possible. Learn more at www.arrow.com Our strategic direction of guiding innovation forward is expressed as Five Years Out, a way of thinking about the tangible future to bridge the gap between what's possible and the practical technologies to make it happen. Learn more at https://www.fiveyearsout.com/ For more job opportunities, please visit https://careers.arrow.com/us/en

Role & responsibilities Designing and developing embedded software and firmware for various electronic products. Mentoring a team of engineers in the development process. Collaborating with cross-functional teams to define product requirements and specifications. Conducting feasibility studies and risk assessments for new projects. Architecting and implementing embedded systems solutions, including hardware and software integration. Writing efficient, maintainable, and scalable code for embedded systems. Performing debugging, testing, and validation of embedded systems. Optimizing system performance, power consumption, and memory usage. Documenting design decisions, processes, and test results. Providing technical guidance and support to junior engineers. Staying updated with emerging technologies and industry trends in embedded systems design and development. Participating in design reviews, project planning, and product lifecycle management activities. Ensuring compliance with industry standards and regulations. Troubleshooting and resolving technical issues throughout the product development lifecycle. Preferred candidate profile Masters / Bachelors degree in Electronics or Electronics & Communication Engineering from reputed university. Minimum 4 years of experience is required for candidates holding a Masters degree in design & development of electronic products, embedded system design, or product application engineering & product validation. For candidates with a Bachelors degree, the minimum requirement is 6 years of experience in the aforementioned fields. High level of experience of embedded C, C++, RTOS, Linux, assembly language, including development of algorithms, flow charts, manipulation of data structures and implementing highly optimized code. Should be able to write firmware from the scratch including device drivers, also able to update & modify existing code. Experienced in following major interfaces, but not limited to, I2C, SPI, USB, LPDDR3, Flash memories, Ethernet, eMMC, UART, LCD, GSM/GPRS, W-Fi, Bluetooth, Modbus TCP, LoRaWAN, ZIGBEE & other communication protocols. Proven experience in embedded systems design with pre-emptive, multitasking real-time Operating systems, STM32, PIC, FPGA, MCS-51, MCS-96, PSoC, Ethernet PHY, ATmega8, ATmega16, LPC2148, Raspberry Pi & other platforms. Familiarity with software configuration management tools, defect tracking tools, and peer review. Excellent knowledge of OS coding techniques, IP protocols, interfaces, and hardware subsystems. Experienced in Proof-of-concept development, Board bring-up testing, Interface testing, System level debugging, Basic knowledge of Digital & Analog circuits and their trouble shooting, Environment & thermal testing. Preferred experience in testing and designing for EMC, PCB prototyping and troubleshooting of complex circuits. Adequate knowledge of reading electrical & timing parameters in datasheets for components. Should be able to operate lab tools: Logic analysers, Oscilloscopes, JTAG/IEC debuggers, and Protocol analysers. Perks and benefits Excellent work culture, 5 Days a week, Group Mediclaim for the employee, spouse & children below 25 years, Group Accident insurance for the employee, Complementary lunch

Job Description In your new role you will: Responsible for Platform level Software Validation for Infineon sAutomotive chipsets Software Validation of device drivers used for Communication orsignal generation/measurements (Eg: SPI, UART, PWM, ADC, DMA etc.) andsafety software in an independent/RTOS environment on Infineon sAutomotive Microcontrollers based on TriCore architecture (AURIX ) orequivalent Support Leads with WBS definition and Estimations. Envisage, implement, institutionalize and maintain the verificationand validation methods and infrastructure (e.g. automation to improvequality and efficiency in terms of cost and time) Drive innovation in the form of new advancements (test methods/tools,test automation, test infrastructure). Institutionalize software test processes compliant with Automotivestandards (e.g. ISO26262, ASPICE). Ownership of reviews - Test Specifications Scripts Your Profile You are best equipped for this task if you have: A minimum of 5-7 years of experience in Device Driver softwaretesting which includes a good know how of standard software developmentLife Cycle Experience in AUTOSAR MCAL and exposure to ISO26262 Embedded system software development or Validation using C, assemblylanguages Experience in the usage of NI, FPGA, oscilloscopes, logic analysers,power benches etc Experience in Embedded System Development tools such as compilers,debuggers (PLS, Lauterbach), static analysers etc Working experience in scripting languages such as Perl, python etc Experience in the development/maintenance of the test automation andcontinuous integration frameworks

Create and implement bare metal drivers for peripherals present in the SOC Closely collaborate with designers & verification engineers to identify and fix issues in design. Sample C/C++ application to run in FPGA Requirements Proven working experience in software/hardware engineering. Experience in hands-on development and troubleshooting on embedded targets. Solid programming experience in Embedded C or C++. Proven experience in embedded systems design with preemptive, multitasking real-time operating systems. Excellent knowledge of OS coding techniques, IP protocols, interfaces and hardware subsystems. Adequate knowledge of reading schematics and data sheets for components. Strong documentation and writing skills. Knowledge of Bluespec System Verilog/ Verilog is a plus but is not a mandatory requirement. FPGA knowledge is added advantage.

Your mission is to create magic on silicon for a brand-new chip company. Design silicon that will be the talk of the town, laying the foundation for our growth into a global semiconductor powerhouse. Outcomes In the first three to six months, you will create, verify, and optimise RTL code for our second chip, which will go into production in early 2025. Over the next few years, you will work on extracting the most from silicon for our upcoming chips. What will your week look like You will be a part of the RTL engineering team and will work on designing, implementing, and verifying digital logic, as well as simulation, emulation, and verification of Vision SoC, our second chip. You might also work on optimising and verifying the RTL code for our first chip, Secure IoT before it goes for mass volume production in mid-2025. Occasionally, you will also have to create and maintain design documentation. In this role, you will be closely coordinating with three teams The verification team, who write test benches to make sure designs meet functional requirements The architects and design leads who define microarchitecture and implement functional blocks The physical design team, who ensure closure on timing, power and area constraints. You will work in the IIT Madras Research Park in Chennai. You will have to invest time and energy every week to improve your technical knowledge of the field, any new developments that occur and your understanding of the tools we use. To that end, many of our employees are pursuing an MS in IIT Madras, and the same option might be open for you. Requirements Technical knowledge of the field is important. The candidate should have an undergraduate degree in electrical engineering, computer science or any relevant field. You need to have a strong understanding of digital design principles, including timing, power, and area optimization. Between 3-5 years of experience in RTL design and implementation on silicon or FPGA. Since you will interact with multiple teams, communication skills are very critical - both written and verbal. Proficiency in Verilog, UVM and System Verilog. Experience with industry-standard EDA tools like Synopsys, Cadence and/or Mentor. We re on a crazy mission to compete with global giants like TI, NXP, etc. So, the candidate must have the inbuilt desire and motivation to take on a tough challenge.

Job Description : - Must have hands on designed/implemented/Integrated DDR controller or DDR Phy design for a project(ASIC or FPGA). - Should be excellent in DDR protocol knowledge. - Must be an expert in micro architecture and RTL coding. Skill set needed - Verilog, SoC & Sub-system RTL Integration, knowledge of industry known standards Interfaces (AXI, AMBA, NOC, Fabric, UCIE, PCIE, SATA, DDR etc. etc.) Scripting : (Shell, python, ruby, perl etc.), CDC & LINT Checkers, Synthesis, LEC, Constraints/SDC understanding, Clocking, UPF, Register roll up. What You'll Do: - You will be responsible for pre-sales support, proposing architecture to customers based on their requirements. - You will work with team to come up with architecture and micro-architecture and work with cross functional team to ensure delivery - You will manage the design / RTL team to achieve the project goals - You will work with customer, provide technical support and provide collaterals agreed upon - You will work with team to achieve flow, methodology improvements to achieve high reuse - You will work with IP vendors to generate / get right configurations of the IP - You will manage team work allocation, schedule, risk mitigation and deliverables from design team. What You'll Need: - 4+ Years of experience in understanding of ARM based architecture, CPU subsystems, interconnect, boot process, memory subsystem, knowledge of Interface IP blocks like PCIe or USB or Ethernet or DDRx controller, QSPI, DMA, or other similar blocks - Good understanding of IPs, integration/application requirement, work with RTL team/vendors to achieve architecture goals - Should have designed one or more ARM based ASIC/SoC and used one or more of PCIe, DDRx, USB, SATA, . - Should have good knowledge of multiple flavors of AMBA bus protocols & interconnect solutions available - Should have good understanding of process / flow to achieve power & performance goals - Should understand and work on all aspects of VLSI development from SoC architecture, micro architecture, RTL coding, RTL quality checks, silicon bring up. - Should have good understanding of requirements from physical design, FPGA, Software, DFT and verification team. - Should have handled a design from Spec to GDS-II - Track design progress, working with cross functional teams, delivering on agreed upon milestones. - Should provide mentoring and support to the team

Job Title: Member of Technical Staff (MTS) DFT Verification Experience: 6+ years Location: Bangalore Job Description: We are seeking a dedicated and experienced Member of Technical Staff (MTS) specializing in DFT Insertion and Verification . The candidate will play a key role in ensuring the robustness and reliability of Tile and SoC designs by implementing and verifying advanced test architectures. Key Responsibilities: Perform SMS (Structural Mode Scan) Insertion and verification at both Tile and SoC levels. Design and verify Memory BIST (Built-In Self-Test) architectures, including initialization and integration. Implement and validate memory repair strategies, including fuse programming (eFuse) and redundancy management. Debug and optimize DFT flows to meet high fault coverage and manufacturability standards. Collaborate with cross-functional teams to ensure seamless DFT integration across various design phases. Analyze test results, resolve silicon and test-related issues, and contribute to yield improvements. Required Skills: Expertise in SMS Insertion and verification for Tile and SoC level designs. Proficiency in Memory BIST architecture, including repair mechanisms and eFuse configuration. Hands-on experience with DFT tools like Mentor Tessent, Synopsys DFT Compiler, or Cadence Modus. Strong scripting skills in Python, Perl, or TCL for automation of test flows. Knowledge of RTL design and debugging (Verilog/VHDL). Excellent problem-solving and analytical skills, especially in debugging silicon failures. Preferred Qualifications: Experience with low-power DFT methodologies and advanced compression techniques. Familiarity with industry standards for JTAG and boundary scan. Hands-on experience with post-silicon validation, bring-up, and characterization.

We are seeking a skilled SoC Frontend Design Engineer to join our integrated circuit (IC) design team. The ideal candidate will be responsible for RTL design, digital logic design, synthesis, linting, timing analysis, and verification for FPGA/ASIC projects. This role requires a deep understanding of VHDL/Verilog, verification methodologies, testbench development, and debugging. The candidate will work closely with cross-functional teams to deliver high-quality, efficient SoC designs. You have: Bachelor s Degree in Electrical, Computer Engineering, or a related field (Master s preferred).3+ years of experience in RTL design, digital logic design, and synthesis. Proficiency in VHDL/Verilog for RTL design. Strong understanding of digital logic design, synthesis, and timing analysis. Experience with linting tools and methodologies. Familiarity with verification methodologies (UVM, System Verilog). Experience in testbench development, simulation, and functional coverage. Strong debugging skills to identify and resolve design issues. Proven track record of successful FPGA/ASIC design projects. Required Tools: Synopsys Design Compiler or Cadence Genus, Mentor Graphics QuestaSim, Spyglass VC It would be nice if you also had: Experience with advanced verification methodologies and tools. Familiarity with high-level synthesis (HLS) tools. Knowledge of scripting languages such as Python, Tcl, or Perl for automation. Develop RTL designs using VHDL/Verilog for FPGA/ASIC projects. Perform digital logic design, synthesis, and timing analysis. Conduct linting and static analysis to ensure code quality. Develop and implement verification methodologies (UVM, System Verilog). Create and maintain testbenches for simulation and functional coverage. Perform simulations and debugging to ensure design correctness. Participate in design reviews and provide feedback to improve design quality.

As a member of Nokia Digital Office - Enterprise Infrastructure & Cloud Services - Service & Operations Management, HWE Platform Service Owner will redefine IT and work on digital optimization transformation. Ensure stability, availability, and high performance of the infrastructure that serves Nokias entire workforce and upholds the technology for almost every interaction of the companys business. You Have: Bachelor s degree in computer science or related field. Experience and understanding of Hardware Engineering environments and processes. Familiarity with HW design and simulation tools and their flows. Familiarity with EDA, SoC/FPGA, PCB, MDA and their associated PLM/PDM systems. It would be nice if you also had: Strong problem and analytical skills, the ability to manage complex projects under strict timelines, as well as the ability to work well in a demanding, dynamic environment and meet overall objectives. Proven project management skills. Data analysis and visualization with PowerBI, Excel, PowerPoint, etc. Office365 tools. Driving projects in cross functional teams, located in different time zones. Will be accountable for ensuring the overall business continuity, quality assurance and performance of the Hardware Engineering Platform services to fulfill the business stakeholder needs and to meet the IT Service Level Agreements. Oversee implementation of tool and process releases (lifecycle management), incident, change and problem management (including RCA approval), execution of requests, demands, support solution and architecture designs jointly with engineering team, process documentation and continuous service improvement of the Hardware Engineering Environments. Support and enhance the platform for our HW Engineering environments which includes all the computing (APPs, GRIDs & DBs), storage solutions, data management, GRID farms, job scheduling systems (Altair Accelerator), remote app hosting, public and private clouds, user group management and associated security protocols. Work closely with the HWE Engineering Team, HWE Service Owners (EDA, MDA, PCB), Service Partners and Global Concept Owners to plan R&D improvements. Ensure understanding of scope and item content and their implications on the end-to-end processes (including costs). Actively seeks for cost saving measures (automation, improved process/flow, etc.), drive change, motivate participants, communication and commit to stakeholders. Balance technical, financial, and interpersonal skills to ensure that all aspects of HWE Platform, HWE Design Environments and customer service are aligned with the organizations strategic goals.

About The Role Develops the logic design, register transfer level (RTL) coding, and simulation for graphics IPs (including graphics, compute, display, and media) required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly across verification hierarchies, drives unit level verification, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high-quality integration of the GPU block. As a principal engineer, recognized as a domain expert who influences and drives technical direction across Intel and industry. Develops and mentors other technical leaders, grows the community, acts as a change agent, and role models Intel values. Aligns organizational goals with technical vision, formulates technical strategy to deliver leadership solutions, and demonstrates a track record of relentless execution in bringing products and technologies to market. Qualifications Minimum Qualifications:BS+15 Years of relevant experience in the semiconductor I industry. experience15+ years of experience in/withVerilog and system verilog, synthesizeable RTL Modern design techniques and energy-efficient/low power logic design and power analysis. 10+ years of experience in/withHaving achieved multiple tape-outs reaching production with first pass silicon. Hands on experience with FPGA emulation, silicon bring-up, characterization and debug Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Position of Trust This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

About our group: This position is part of Seagate Research Group (SRG). Seagate delivers advanced digital storage solutions to meet the needs of todays consumers and tomorrows applications. Through technology, leadership and innovation, Seagate continues to help individuals and businesses maximize the potential of their digital content in an ever-evolving, on-demand world. About the role - you will: Work full time on projects at Pune in assisting Seagate Research Architect/leads in the area of most cutting-edge research in storage technologies Responsible for investigating emerging technologies in storing data efficiently, which create data in new frontiers from AI/ML/mobility. Potentially explore new mechanisms in electronic hardware modeling and prototyping in processing the data using upcoming technologies such as computational storage securely. Your work includes but would not be limited to, survey and process public and enterprise forums to help build models around these technologies, generate new ideas and conceptualize them and with the help of senior engineers in the team, contribute in the development of architecture towards building proofs of concepts. Research/investigate emerging technologies in storage components and system, Data creation models and storage security Document current and future storage architectures for different applications Provide research intelligence for future Seagate products or create reference architectures Work with subject matter experts at all Seagate (worldwide) sites Create internal and external research papers and work with your affiliated school to bring academic research in these areas for applications in storage industry About you: Creative, independent and self-starter individual with excellent written and interpersonal communication who would be looking forward to work in corporate set up Must be authorized to work in India while pursing education Teamwork is a core competency at Seagate, individual must be able to work and communicate effectively with a diverse group of engineers Must have demonstrated ability to study a functional area in depth Ability to present to colleagues and partner Your experience includes: Working knowledge of Unix-based and Windows Operating Systems Graduate School Research level experience with innovative techniques in AI/ML as well as Exposure to storage domain and FPGA based systems are added plus

What youll do Led by ex-traders and ex-engineers, our renowned in-house education team will guide you through the intricacies of market making. You will be immersed in a mix of hands-on and classroom learning, empowering you to thrive in the world of trading and technology. As part of the FutureFocus program, you ll have the opportunity to: Kickstart your journey as a developer and explore our tech career pathways. Discover the cutting-edge techniques that keep us at the forefront of the global financial markets and see our world-class trading systems in action. Learn the core fundamentals of trading and build trading strategies for deployment in a virtual market. Connect with recent graduates and hear their personal experiences. Receive mentorship and support from our in-house trainers and senior developers, who are committed to ensuring you have the guidance and support needed to succeed. Experience Optivers culture and enjoy our incredible perks, including daily breakfast, lunch and coffee, weekly massages and more. Who you are A pre-penultimate student (graduating in 2027), studying at an Indian university. All degree backgrounds are considered. An inquisitive thinker, with a passion for quantitative problems and working in collaborative, dynamic environments. Holds superior quantitative and logical reasoning skills, and enjoys working on an array of problems, with a strong focus on results. Excited to test yourself in one of the most dynamic areas of the financial market.

About Astrogate Labs Astrogate Labs is a space-technology start-up based in Bengaluru, building core technologies in laser communication terminals and networks for small-satellites. Astrogate Labs aims to simplify, reduce cost of communication, and enable satellites send more data to ground. We have developed one of the industry s smallest optical communication terminals targeted for small satellite use, further scaling our products and aiming for our first satellite mission. We aim to revolutionize satellite communications and support the growing satellite downlink needs with a network of optical ground stations and in-space relays using the technologies developed in-house. We are looking for bright and passionate folks like you to join our exceptional team. Job Title: FPGA Design Engineer Qualification: ME/MTECH in Electronics & Communication or Electrical engineering or any other related field with 3+ years of relevant experience, although this is secondary to relevant experience. Job Responsibilities: We are looking for folks who is excited to work with corss-functional team and develop custom FPGA module/ cores for our laser/ optical communication systems. Design, Implement, Test and Integrate RTL FPGA hardware for free space laser/ optical communication applications. Write custom FPGA IP blocks and PS code for target hardware. Write testbenches to test the target hardware by integrating other system peripherals. Integrate designs onto FPGA/SoC platforms Bring up and validate devices that communicate to and fly in space Digital signal processing of sensor data. Participate in component selection and design tradeoff analysis. Document and manage configuration of firmware Contribute to peer and external design reviews Required Skills/Experience: 2+ years of experience in FPGA Design, Implementation & Verification. Proficient with Verilog/VHDL Experience in FPGA Implementation Tools (XILINX Vivado), Zynq SoC s. Deep understanding of digital design concepts, communication systems, various modulation, encoding & forward error correction techniques. Good knowledge in C/C++ and MATLAB Experience with simulation, verification, and test of FPGA firmware and embedded systems Hardware debug experience, including familiarity with tools such as the oscilloscopes, logic analyzers, and signal generators. Familiar with common electronic components and comfortable reading circuit design schematics and contributing to electronics hardware design discussions Must be an independent thinker and motivated to work within a multidisciplinary team. Perks: Health Insurance coverage Association & supervision by industry experts and senior members. Publish research on behalf of Astrogate Labs Other early-stage company benefits including ESOPs Team oriented work culture for the development of extraordinary space products Prior experience in aerospace/ space technology projects is an added advantage. If you like working in a fast paced environment in a multi-disciplinary team on developing and maturing state-of-the-art Lasercomm systems, then this role might be for you.

Role : LabVIEW Developer Client :Robert Bosch Location : Koramangala, Bangalore Hands on experience in Labview Design Patterns and Labview architecture Experience in Labview programming Knowledge in Communication protocols, preferably in CAN/SPI Basic knowledge on Hardware instruments like DMM, Oscilloscope, Power Supplies, etc Should perform tasks independently and execute it on time Criteria Strong knowledge in NI LabVIEW design pattern, NI LabVIEW RT & FPGA. Experienced in ATE development. Experienced in System testing, Integration testing and Functional testing. Basic Knowledge on Hardware s (Oscilloscope, Various power supplies, DMM , NI DAQ, Relays, FG and other instruments) Experienced with implementing embedded and serial communication protocols (I2C, RS-485, RS-232, CAN, MODBUS) Experienced with networking protocols TCP, UDP,GPIB, BLE & Wi-Fi Familiar with basic concepts of Software Quality and Process. Familiar with testing methodology and test plan creation. System verification of embedded products with graphical user interface and hardware I/OS. Strong written and verbal communication skills, with attention to detail and thoroughness. English language proficiency spoken and written

Development using LabView environment for test and measurement, motion control and Vision applications. Sound knowledge and experience working with Multifunction DAQ, FPGA, PCI and PXI chassis. Hands on exp in developing GUI Testing and validation of code, occasionally onsite with customer, Installation and Commissioning at Client End Trouble shooting and debugging of existing LabView/PLC/HMI/PC based test benches. Customer Support onsite/offsite of implemented code and hardware Write code to interface with internal and external hardware for data acquisition Maintenance of code Software Documentation Test software for automated test of products Processing of test data using LabVIEW code Report on results of data processing

We are looking for an experienced Engineer with extensive experience with FPGA and emulation tasks of SoC preferably for Power related applications that has a thorough understanding of Xilinx Architecture and Timing closure strategies with the Verilog RTL coding skills and debug capabilities Exp-7

We are looking for an experienced Engineer with extensive experience with FPGA and emulation tasks of SoC preferably for Power related applications that has a thorough understanding of Xilinx Architecture and Timing closure strategies with the Verilog RTL coding skills and debug capabilities Exp-7

Siplont Sytems Pvt Ltd is looking for SoC Verification Engineer to join our dynamic team and embark on a rewarding career journey. Analyzing customer needs to determine appropriate solutions for complex technical issues Creating technical diagrams, flowcharts, formulas, and other written documentation to support projects Providing guidance to junior engineers on projects within their areas of expertise Conducting research on new technologies and products in order to recommend improvements to current processes Developing designs for new products or systems based on customer specifications Researching existing technologies to determine how they could be applied in new ways to solve problems Reviewing existing products or concepts to ensure compliance with industry standards, regulations, and company policies Preparing proposals for new projects, identifying potential problems, and proposing solutions Estimating costs and scheduling requirements for projects and evaluating results

Expertise in C ++ / C Programming and Yocto Embedded Linux, with goodProficiency. Desired skills: 1. Experience working with Embedded LinuxBSP (Board Support Package) on embedded platforms. 2. Strong knowledge for Linux device drivers (Camera), Linux Kernel Programming, Linux Kernel Internals, Yocto / Build rootor any other build systems 3. Experience working with differentembedded platform like ARM/PowerPC processor and DSP based Texas InstrumentsTDA4, TDA3x, TDA2X, NXP,QUALCOMM Adas platforms Qualcomm, TI, NXP, 4. Experience of Board bring-up, bootloadercustomization in Linux/ QNX/ SYSBIOS/ Vxworks/ Integrity/ ROS, any other POSIXRTOS 5. Extensive knowledge of graphics pipeline ,reprojection and advanced rendering techniques, 6. computer vision pipelines, machinelearning methods and/or camera pipelines 7.Implement embedded SW in LINUXenvironment for our ADAS products 8.Design and Develop LINUX SW related tocomputer vision, TDA4xx SW integration. 9. Expertise in LINUX application processdevelopment / RTOS and Debugging experience on memory management, taskmanagement etc 10 Design and build the image pipeline from thecamera to the display / drivers for camera, radars and display 11. Able to handle Camera, GPU, CPU, SOCInter processor communications and constructing video pipeline 12. Familiar with the integration of cameraalgorithms on mobile or PC embedded systems pipeline and ensure the imagequality optimization of the integration for the product. 13. Deep understanding of principles ofCamera Sensors and camera modules for GPU/FPGA platforms. 14. Experience on coreDump and low-levelLinux debug tools (sTrace, and debugs) 15. Familiarity working with development toolslike oscilloscope, protocol analyzer, emulator, signal generator, JTAGprogrammer, GIT, SVN, JIRA

Who You ll Work With Our Hardware Design Engineering team is at the forefront of developing high-speed networking and Ethernet products used in Enterprise campuses, hyperscale datacenters and bleeding edge AI clusters. The team is responsible for the end-to-end design and development of advanced hardware solutions that meet the demands of modern networking environments. What You ll Do: You ll lead the hardware design process for high-performance networking products, from creating functional specifications and schematic design to collaborating with eCAD teams on PCB layout. You ll work with PCB vendors, oversee prototypes through to production, and ensure high yield in manufacturing. Additionally, you ll troubleshoot system issues with software and test teams, while mentoring junior engineers to drive innovation in high-speed networking solutions. Job Responsibilities Candidates for this position would be responsible for the entire hardware design process: Authoring Functional Specifications for high density Ethernet switches Selecting and Qualifying Components Schematic Capture (both flat and hierarchical) Working closely with eCAD teams on PCB layout and component footprints Specifying PCB stackup and fabrication details with various PCB vendors Working closely with local and overseas Contract Manufacturers (CM), from proto through production Lab bring up and debug of prototypes Driving complex system debug between software, hardware, and test teams Training CM for high yield test and manufacturing Guiding groups of engineers and mentoring younger engineers BSEE or MSEE 5+ years of relevant experience in hardware engineering Embedded x86/ARM system design is highly desirable Experience working with multi-phase DC/DC s for high current, high transient loads Experie

SOC Verification engineers with 3+ years of experience Knowledge of ARM architecture, CPU fundamentals & Cache coherency Experience with C/C++, assembly, and scripting languages. Familiarity with low-power design and verification Develop CDV UVM verification environments at system level Verify CPU connectivity to IP blocks Develop SoC test plans and test cases and track metrics including code and functional covera Job Requirement: Bachelors or Masters in EE/CS or related field 3+ years of SoC in ASIC/FPGA verification experience Proficiency in SV and UVM Experience with simulation, emulation, and formal verification Strong debugging and problem-solving skills Experience (years) : 3+ Year Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Hiring FPGA Engineers Multiple Openings! We are looking for skilled FPGA Engineers across different experience levels to join our team. If you have expertise in RTL design, FPGA architecture, and board bring-up , apply now! Open Positions: Senior FPGA Engineer (7-10 years experience) Expertise in low-latency FPGA design Strong understanding of FPGA architecture Excellent RTL design and coding skills Proficiency in timing analysis FPGA Engineer (2-4 years experience) (Work from office – 5 days/week) Solid knowledge of FPGA architecture Strong RTL design and coding skills Experience in FPGA and board bring-up FPGA Prototyping Engineer (5-8 years experience) Hands-on experience in FPGA prototyping for ASIC Ability to convert ASIC RTL to FPGA Excellent RTL design and coding skills Good system understanding, including software integration Experience with board bring-up Interested candidates can apply now! Let me know if you need any further refinements!

Proficient in RTL design using Verilog/SystemVerilog or VHDL In-depth knowledge of FPGA architecture and development flows (synthesis, P&R, timing analysis) Familiarity with high-speed interfaces and protocols like PCIe, Ethernet, DDR, AXI, AHB, SPI Required Candidate profile Experience with debugging tools like ChipScope, SignalTap, Logic Analyzer Proficiency in scripting languages like Python, Tcl, or Perl for automation of FPGA workflows