4 - 9 years
6 - 11 Lacs
Posted:15 hours ago|
Platform:
Work from Office
Full Time
Approved TP SR
ERS/ERS/2025/2809400
BR
1644122BR
Total Open Positions
2
Band
E1.2
Experience
4 Years
Skill
Signal Power Integrity SI/PI
SOW signed Yes / No
In Progress
Customer
Renesas
Customer BGV Yes / No
No
Tentative Project Timeline
6 Months
Work Location
HCL Chennai/Bangalore
Detailed JD
Signal Integrity Analysis SI Serial Links and DDR4/5; Signal Quality, Losses Crosstalk; HFSS HSPICE Tools; Both PKG PCB Experience
Power Integrity Analysis DC AC Analysis; Decap Loop Inductance Optimization; DDR4/5; HFSS/SIWave HSPICE Tools; Both PKG PCB Experience
Han Digital Solution
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