Senior Principal Engineer

Your Team, Your Impact

What You Can Expect

• Lead the DV execution and sign-off for the entire IP, Subsystem and SoC
• Define and drive improvements in DV processes for efficient and high-quality execution
• Collaborate with IP, Subsystem, and SoC teams on test plan creation, testbench architecture, and milestone reviews
• Work closely with Design and DV teams across IP, Subsystem, and SoC levels for test plan development, execution, debug, coverage closure, and gate-level simulations
• Coordinate with cross-functional teams including Architecture, Chip Lead, Emulation, and Program Management to drive SoC-level DV execution
• Partner with Silicon bring-up and Firmware teams to support post-silicon validation and bring-up activities
• Own and debug simulation failures to identify and resolve root causes
• Architect and implement simulation testbenches using UVM
• Develop and execute test plans to verify design correctness and performance
• Collaborate with logic designers for thorough verification coverage and closure

What Were Looking For

• Bachelor s degree in CS/EE with 22+ years of relevant experience or Master s degree in CS/EE with 20+ years of relevant experience
• Strong background in IP and SoC verification methodologies and testbench development using Verilog, SystemVerilog, UVM, and C/C++
• Deep understanding of verification techniques including object-oriented programming, white-box/black-box testing, directed/random testing, formal verification, coverage analysis, and gate-level simulations
• Proven experience in DV sign-off for Functional, Power, Performance, and Security metrics
• Strong knowledge of Unix/Linux environments; scripting experience in Shell, Perl, or Python is a plus
• Demonstrated analytical and problem-solving capabilities
• Ability to manage multiple tasks in a fast-paced, dynamic environment
• Excellent interpersonal, teamwork, and communication skills
• Proven ability to interface across all levels of internal and external stakeholders
• Experience leading DV execution and sign-off for complex SoCs
• Hands-on involvement in 10+ successful tape-outs and post-silicon bring-up