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DFT (Design For testability)- Staff / Senior Staff

7 - 12 years

15 - 30 Lacs

Noida

Posted:3 months ago| Platform: Naukri logo

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Skills Required

SOC Design For Testability Scan Insertion DFT EDA Tools Perl Scripting JTAG Atpg Tessent System on a Chip TCL Mbist Python

Work Mode

Hybrid

Job Type

Full Time

Job Description

Hiring: DFT Engineer (Design for testability) for Staff/Sr Staff positions Location: Noida (Hybrid 3 Days Work from Office) Experience: 7 to 15 years We are looking for a technical leader to drive the DFT aspects of high-performance compute SOC/MCU development. The candidate must be experienced, hands-on and have robust understanding of testability features including SSN, MBIST, LBIST, Scan Insertion, ATPG, GLS and post silicon debug on automotive grade SOCs. Key Responsibilities: Hierarchical scan insertion and SSN-based ATPG flow MBIST integration & verification at RTL level LBIST RTL integration, verification, and GLS enablement Implementation & verification of IEEE 1149.1 JTAG, IJTAG Post-silicon debug for DFT patterns Close collaboration with RTL, PD, and Verification teams Proficiency in scripting languages ( TCL, Perl, or Python ) Apply Now! Click on the Apply button or share your resume with Heena at heena.k@randstad.in Tag your connections who might be interested in this exciting opportunity!

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Staffing and Recruiting

Atlanta GA

1001-5000 Employees

893 Jobs

    Key People

  • Linda Galipeau

    CEO - Randstad North America

  • Tom Hart

    Chief Financial Officer (CFO)

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