Job
Description
You are a highly skilled and experienced engineer with a deep understanding of synthesis, timing closure, power optimization, and constraints management. You have a proven track record of working on advanced nodes under 5nm and are proficient in low-power, high-performance design. Your familiarity with RTL, DFT, LDRC, TCM, VCLP, and PTPX gives you an edge in tackling complex design challenges. You are adept at scripting languages such as TCL, Perl, and Python, and hold a BS or MS in Electrical Engineering or a related field with over 9 years of relevant experience. You thrive in a dynamic environment, constantly seeking to push the boundaries of technology and improve quality of results. Your ability to work both independently and collaboratively makes you an invaluable asset to any team. What You ll Be Doing: Developing innovative methodologies for implementing high-performance CPUs, GPUs, and interface IPs. Utilizing advanced technologies and tool features to enhance quality of results and streamline the implementation process. Contributing to the development and implementation of power, performance, and area (PPA) methodologies for complex IPs. Working with industry-leading Synopsys tools such as RTLA and Fusion Compiler to solve critical design challenges. Collaborating with a global team to stay ahead of technological advancements and design complexities. Driving continuous improvement in PPA and turnaround time (TAT) metrics. The Impact You Will Have: Advancing the state-of-the-art in high-performance core and IP implementation. Enhancing the performance and efficiency of Synopsys design methodologies and tools. Enabling the development of cutting-edge semiconductor technologies at advanced nodes. Contributing to the successful delivery of high-quality, high-performance IPs to the market. Driving innovation and pushing the boundaries of what is possible in chip design. Supporting Synopsys mission to lead in chip design, verification, and IP integration. What You ll Need: Deep knowledge of synthesis, timing closure, power optimization, and constraints management. Experience with low-power, high-performance design at advanced nodes under 5nm. Proficiency in RTL, DFT, LDRC, TCM, VCLP, and PTPX. Familiarity with scripting languages such as TCL, Perl, and Python. BS or MS in Electrical Engineering or a related field with 9+ years of relevant experience.
