Design Verification Engineer (Formal)

Position: Formal verification Engineer

About the Role

Experience with Formal Verification (e.g., sequential equivalence checking, Security Path verification, connectivity, low power and Formal property verification).

Responsibilities

• Experience with programming languages (e.g., Python/Perl and TCL).
• Experience with at least one formal verification tool (e.g., Cadence Jasper, Synopsys VC-Formal).
• Expertise in property specification languages (e.g., SVA, PSL).
• Proficiency in HDLs such as System Verilog, Verilog or VHDL.

Qualifications

• Experience-4+ years

Required Skills

• Formal Verification

• Programming languages (Python/Perl and TCL)

• Formal verification tools (Cadence Jasper, Synopsys VC-Formal)

• Property specification languages (SVA, PSL)

• HDLs (System Verilog, Verilog or VHDL)

Preferred Skills

• None specified

Pay range and compensation package

• Location-

  Pune

Equal Opportunity Statement

We are committed to diversity and inclusivity.