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CPU Physical Design CAD Engineer

CPU Physical Design CAD Engineer

Qualcomm

6 - 11 years

11 - 15 Lacs

bengaluru

Posted:None| Platform:

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Skills Required

python digital design timing analysis physical verification tcl synthesis sta physical design eda static timing analysis primetime cad hardware engineering lvs innovus cadence floorplan floor planning silicon timing closure drc pnr placement

Work Mode

Work from Office

Job Type

Full Time

Job Description

General Summary:

NUVIA is now part of Qualcomm. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability.

Minimum Qualifications:

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.As CPU Physical Design CAD engineer, you will build and support the worlds best implementation tools and flows. Your tools and flows will ensure our custom CPUs have industry-leading power, performance and area.Roles and Responsibilities

Develop, integrate and release new features in our high-performance place-and-route CAD flow
Architect and recommend methodology improvements to ensure our silicon has the best power, performance and area
Maintain, support and debug implementation flows, and resolve project-specific issues
Work closely with worldwide CPU physical design teams, and provide methodology guidance, tools/flows support and help achieve class-leading PPA.
Work with EDA vendors to define roadmap and to resolve tool issues

Preferred Qualifications:

Bachelors/Masters degree in Electrical/Electronics Engineering or Computer Science
Ten+ years of hands-on experience in place-and-route of high-performance chips - either in a design or CAD role
High level of proficiency in Tcl as well as Python
Experience with automation
Experience with a wide variety of Physical Design tasks - ranging all the way from place-and-route, analysis, timing sign-off and PDV
Experience with advanced technology nodes (5nm or lower)
Solid understanding of digital design, timing analysis and physical verification
Strong user of industry-standard place-and-route tools such as Cadence Innovus
Proven track record of managing and regressing place-and-route flows

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CPU Physical Design CAD Engineer