Chip Lead (15+ Years of expereince)

Job Description

Responsibilities: Leading the program end-to-end from architecture to tapeout. Work with systems teams to define architecture and design specifications. Work with Design teams to define micro-architecture/ design implementation (module level SOC level). Ensure compliance to the company s design process/ design flows. Ensure design maturity at intermediate milestones, maintaining schedule cognizance, and adhering to defined quality metrics throughout the development process. Overseeing the development of RTL code and ensuring its correctness. Reviewing the verification process verification scope/plan, including functional, coverage-driven, and power-aware verification. Reviewing the Emulation plan/ scope to help define Tape-out gating items Coordinating with DFT Physical design teams to ensure successful implementation and tape-out. Conducting reviews for performance tests to evaluate system stability, scalability, and reliability. Addressing the complexity of multi-die solutions, including inter-die communication, power management, and thermal challenges. Designing and implementing chips targeting datacenter applications, focusing on high performance, low power consumption, and scalability. Collaborating with cross-functional teams across sites for smooth execution of the program, including post-Si debugs Providing technical guidance and mentorship to junior engineers. Ensuring compliance with industry standards and best practices. What Were Looking For Bachelors or Masters degree in Electrical or Computer Science Engineering or a related field. 20+ years of technical experience with 5+ tapeouts as a Chip lead. Proven experience in leading RTL2GDSII programs. Strong background in RTL design, verification methodologies, and physical design. Proficiency in scripting languages (PERL/Python) and EDA tools. Solid understanding of system and processor architecture, advanced memory, and IO technologies. Experience with multi-die solutions and addressing their associated complexities. Knowledge of designing chips for datacenter applications, including performance optimization and power management. Excellent self-motivation, communication, problem-solving, and teamwork skills. Show more Show less