Job
Description
**Role Overview:** You will be part of a team that develops custom silicon solutions for Google's direct-to-consumer products, contributing to the innovation behind widely-loved products. Your role will involve shaping the next generation of hardware experiences, focusing on performance, efficiency, and integration. As a member of the team designing the SoC and Subsystem, you will be responsible for all phases of design and implementation, from working with architects on microarchitecture specifications to collaborating with verification and Physical Design teams for successful tape-out. **Key Responsibilities:** - Define the block-level design document, including interface protocol, block diagram, transaction flow, and pipeline. - Perform RTL coding, function/performance simulation debug, and Lint/CDC/FV/UPF checks. - Participate in test plan development and coverage analysis for block and ASIC-level verification. - Collaborate and communicate effectively with multi-disciplined and multi-site teams. **Qualifications Required:** - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. - 4 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog. - Experience with logic synthesis techniques, optimization of RTL code, performance, power, and low-power design techniques. - Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science (preferred). - Experience with scripting languages like Perl or Python (preferred). - Experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT (preferred). - Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture (preferred). - Knowledge of memory compression, fabric, coherence, cache, or DRAM (preferred). (Note: The additional details of the company were not explicitly mentioned in the provided job description.) **Role Overview:** You will be part of a team that develops custom silicon solutions for Google's direct-to-consumer products, contributing to the innovation behind widely-loved products. Your role will involve shaping the next generation of hardware experiences, focusing on performance, efficiency, and integration. As a member of the team designing the SoC and Subsystem, you will be responsible for all phases of design and implementation, from working with architects on microarchitecture specifications to collaborating with verification and Physical Design teams for successful tape-out. **Key Responsibilities:** - Define the block-level design document, including interface protocol, block diagram, transaction flow, and pipeline. - Perform RTL coding, function/performance simulation debug, and Lint/CDC/FV/UPF checks. - Participate in test plan development and coverage analysis for block and ASIC-level verification. - Collaborate and communicate effectively with multi-disciplined and multi-site teams. **Qualifications Required:** - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. - 4 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog. - Experience with logic synthesis techniques, optimization of RTL code, performance, power, and low-power design techniques. - Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science (preferred). - Experience with scripting languages like Perl or Python (preferred). - Experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT (preferred). - Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture (preferred). - Knowledge of memory compression, fabric, coherence, cache, or DRAM (preferred). (Note: The additional details of the company were not explicitly mentioned in the provided job description.)
