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Advanced Micro Devices, Inc
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ASIC RTL Design/Integration Lead

ASIC RTL Design/Integration Lead

Name: Jobpe
Address: T-Hub, Plot No 1/C, Sy No 83/1, Raidurgam panmaktha, Knowledge City Rd, Hyderabad, Telangana, 500081, IN
Telephone: +91-83339-09630
Price range: Free

Advanced Micro Devices, Inc

12 - 17 years

45 - 50 Lacs

bengaluru

Posted:4 hours ago| Platform:

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Skills Required

asic dft linux soc perl system verilog gaming python physical design recruitment

Work Mode

Work from Office

Job Type

Full Time

Job Description

SMTS SILICON DESIGN ENGINEER - Custom Silicon ASIC RTL Design/Integration Lead

THE ROLE:

The focus of this role in the AECG ASIC organization is to provide technical leadership in developing microarchitecture, implementing the design in RTL, RTL Integration etc. ensuring quality (design checks and verification reviews) and PD support for next generation ASICs

THE PERSON:

You have a passion for modern, complex SoC architecture with various IO peripherals and heterogenous processor systems and digital design & verification in general. You are a team player who has excellent communication skills and experience collaborating in a corporate environment with other architects & engineers located in different sites/time-zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:

Define and specify micro-architecture of ASIC building blocks and necessary infrastructure based on architecture, PPA, DFT, Functional Safety requirements
RTL design and debug of complex blocks in Verilog / System Verilog
Analyze design metrics and make implementation choices to optimize PPA
RTL Integration
Work with implementation, verification and physical design teams to achieve high quality design and successful tape out
Address customer problems through innovative enhancements to product architecture/ micro-architecture
Collaborate with cross-functional teams to solve novel problems across multiple functional areas in development of clocking features and/or algorithms
Lead internal and external teams for RTL design

PREFERRED EXPERIENCE:

Strong foundation in SoC architecture and processor systems with proven years of experience
Good analytical problem solving, and attention to details
Excellent written and verbal communication skills
Knowledge of CPU, AXI Interconnect, and I/O peripherals
Knowledge of SOC development flow and accelerator IP
Must have worked with third party contractors
ASIC design flow and direct experience with ASIC design in sub-7nm technology nodes
Digital design and experience with RTL design in Verilog/System Verilog
Circuit timing/STA, and practical experience with Prime Time or equivalent tools
Low power digital design and analysis
Modern SOC tools including Spyglass, Questa CDC, Cadence Conformal, VCS simulation
TCL, Perl, Python scripting
Version control systems such as Perforce, ICManage or Git
Strong verbal and written communication skills
Ability to organize and present complex technical information
Fluent in working with Linux environment

ACADEMIC CREDENTIALS:

BS, MS or PhD degree in in Electrical Engineering or Computer Science. 12+years of experience in an ASIC leadership role leading to an understanding of end-end development.
Experience in leading complex subsystem or SOC level integration, quality cleanup and delivery to DV, physical design teams
Strong understanding of SOC globals like clocking, reset, boot and power management flows, low power design techniques, security
Strong technical leader who communicates well with great collaboration skills
Good understanding of other domains like pre-si verification, Synthesis, physical design

#LI-SR4

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ASIC RTL Design/Integration Lead