ASIC RTL Design Engineer

You are looking for your next big challenge in ASIC Design and we are hiring ASIC Design Engineers with 8-15 years of experience to join our team in Hyderabad. If you have expertise in RTL design, Verilog coding, SoC integration, synthesis, timing closure, and have completed at least one tape-out cycle, we would love to connect with you. **Role Overview:** - Seeking ASIC Design Engineers with 8-15 years of experience. - Expertise in RTL design, Verilog coding, SoC integration, synthesis, timing closure required. - Must have completed at least one tape-out cycle. **Key Responsibilities:** - RTL design for ASIC projects. - Verilog coding for complex designs. - Integration of SoC components. - Synthesis and timing closure activities. - Complete at least one tape-out cycle successfully. **Qualifications Required:** - Bachelor's/Master's degree in Electrical/Electronics Engineering or related field. - 8-15 years of experience in ASIC Design. - Proficiency in RTL design, Verilog coding, SoC integration. - Strong understanding of synthesis and timing closure processes. - Experience in completing tape-out cycles. Please apply now or reach out directly to sivajyothi.adhikari@proxelera.com for further information. You are looking for your next big challenge in ASIC Design and we are hiring ASIC Design Engineers with 8-15 years of experience to join our team in Hyderabad. If you have expertise in RTL design, Verilog coding, SoC integration, synthesis, timing closure, and have completed at least one tape-out cycle, we would love to connect with you. **Role Overview:** - Seeking ASIC Design Engineers with 8-15 years of experience. - Expertise in RTL design, Verilog coding, SoC integration, synthesis, timing closure required. - Must have completed at least one tape-out cycle. **Key Responsibilities:** - RTL design for ASIC projects. - Verilog coding for complex designs. - Integration of SoC components. - Synthesis and timing closure activities. - Complete at least one tape-out cycle successfully. **Qualifications Required:** - Bachelor's/Master's degree in Electrical/Electronics Engineering or related field. - 8-15 years of experience in ASIC Design. - Proficiency in RTL design, Verilog coding, SoC integration. - Strong understanding of synthesis and timing closure processes. - Experience in completing tape-out cycles. Please apply now or reach out directly to sivajyothi.adhikari@proxelera.com for further information.