Asic Rtl Design Engineer

5 - 10 years

15 - 30 Lacs

Posted:1 day ago| Platform: Naukri logo

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Job Type

Full Time

Job Description

Job Title

ASIC Microarchitecture & RTL Design Engineer

Location

Bangalore IBC Knowledge Park

Experience

5 to 15 Years (Overall ASIC RTL Experience)

Notice Period

Immediate to 30 Days (Highly Preferred)

Job Summary

highly skilled ASIC Microarchitecture & RTL Design Engineer

architecture, verification, physical design, and software teams

Key Responsibilities

ASIC Microarchitecture

  • Define and own

    microarchitecture specifications

    based on high-level architecture and system requirements
  • Translate system-level requirements into

    detailed block-level microarchitecture

  • Perform

    microarchitecture trade-off analysis

    (performance, power, area, latency)
  • Develop

    state machines, pipelines, arbitration logic, buffering, and control paths

  • Review and sign off

    microarchitecture documents and design specifications

RTL Design & Integration

  • Design, implement, and maintain

    high-quality synthesizable RTL

    using

    SystemVerilog / Verilog

  • Develop

    parameterized, reusable RTL blocks

    suitable for IP and SoC integration
  • Ensure RTL compliance with

    ASIC coding guidelines and best practices

  • Perform block-level and subsystem-level RTL integration
  • Collaborate closely with

    verification teams

    to ensure functional completeness and coverage closure

ASIC Frontend Flow Ownership

  • Support and debug issues related to:
    • RTL linting
    • CDC/RDC analysis
    • Logic synthesis
    • LEC and frontend signoff readiness
  • Work closely with

    physical design teams

    to address synthesis, timing, and ECO-related issues
  • Participate in

    design reviews, code reviews, and signoff checkpoints

Cross-Functional Collaboration

  • Interface with

    system architects, verification, PD, DFT, and software teams

  • Support IP/SoC bring-up, debugging, and silicon validation activities
  • Contribute to continuous improvement of

    RTL quality, microarchitecture robustness, and design methodologies

Experience & Technical Skills

  • 5–15 years of hands-on ASIC RTL design experience

  • Minimum 3 years of proven microarchitecture ownership experience

  • Strong proficiency in

    SystemVerilog / Verilog

  • Strong understanding of:
    • Pipelined and FSM-based microarchitectures
    • Multi-clock and reset domain designs
    • Performance, power, and area trade-offs
  • Experience working on

    complex IPs or SoC-level designs

Desired / Good-to-Have Skills

  • Experience with industry-standard ASIC frontend tools (e.g., DC/Genus, SpyGlass, Conformal)
  • Understanding of

    low-power design concepts (UPF, clock gating)

  • Familiarity with

    AMBA protocols (AXI/AHB/APB)

  • Experience with

    performance modeling or architectural simulations

  • Exposure to advanced technology nodes (16nm preferred)

Soft Skills

  • Strong analytical and problem-solving skills
  • Excellent communication and technical documentation abilities
  • Ability to work independently and in cross-functional global teams
  • Ownership mindset with strong attention to design quality and timelines

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