ASIC Digital Design, Sr Staff Engineer

Role Overview: As a Senior RTL Design Lead at Synopsys, you will play a crucial role in leading complex ASIC digital subsystems from concept to silicon. You will be responsible for crafting subsystem architectures, developing functional specifications, implementing micro-architectures, and ensuring compliance with best RTL coding practices. Your expertise in industry-standard protocols such as PCIe, DDR, UFS, USB, and AMBA will be essential in integrating them within subsystem designs. Additionally, you will mentor junior engineers, participate in technical reviews, and drive innovation within the team. Key Responsibilities: - Lead the complete subsystem lifecycle, from requirements gathering to final release phases. - Develop comprehensive functional specifications and ensure compliance with best RTL coding practices. - Drive RTL quality checks, linting, CDC, and ensure bug-free first silicon delivery. - Collaborate closely with verification, DFT, and physical implementation teams for seamless project execution. - Integrate and support standard protocols such as PCIe, DDR, UFS, USB, and AMBA within subsystem designs. - Apply low power design methodologies and ensure DFT requirements are met at the architectural level. - Mentor junior engineers and participate in technical reviews to foster innovation and knowledge sharing. Qualifications Required: - Minimum 8 years of hands-on experience in RTL design and subsystem architecture for complex ASIC/SoC projects. - Proficiency with standard protocols including PCIe, DDR, UFS, USB, and AMBA. - Demonstrated expertise in low power design methodologies and DFT architecture. - Strong experience with RTL coding (Verilog/SystemVerilog), linting, CDC, and formal verification tools. - Proven ability to lead cross-functional teams through all project phases, from specification to silicon. (Note: The additional details of the company provided in the job description have been omitted as they were not explicitly defined),