6 Physical Implementation Jobs

Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Physical Design Good to have skills : NA Minimum 5 Year(s) Of Experience Is Required Educational Qualification : 15 years full time education Summary: As a Software Development Engineer, you will engage in a dynamic work environment where you will analyze, design, code, and test various components of application code across multiple clients. Your typical day will involve collaborating with team members to ensure the successful implementation of software solutions, performing maintenance and enhancements, and contributing to the overall development process. You will be responsible for delivering high-quality code while adhering to project timelines and standards, ensuring that the applications meet the needs of the clients effectively. Roles & Responsibilities: Undertake block PD closure in advanced technology nodes viz. 7nm, 3nm, 2nm etc. Responsibilities include physical design implementation for multi-hierarchy low-power designs including physical-aware logic synthesis, floorplan, place & route, clock tree synthesis, routing, static timing analysis, IR Drop, EM, and physical verification. Support & resolve design and flow issues related to physical design implementation, identify potential solutions, and drive & implement methodology improvements. Professional & Technical Skills: - Must To Have Skills: Proficiency in Physical Design. - Strong understanding of digital circuit design and layout. - Experience with design verification and validation techniques. - Familiarity with industry-standard design tools and software. - Ability to troubleshoot and resolve design-related issues effectively. Proficiency in advanced synthesis, physical implementation & timing closure techniques to achieve aggressive low power, area, and timing goals. Experience in running physical-aware logic synthesis and achieving optimal synthesis QoR on low power designs. Knowledge of static timing analysis, defining timing constraints and exceptions, corners/voltage definitions. Experience working with EDA tools Redhawk/Voltus. Additional Information: - Bachelor&aposs degree in Electrical Engineering or Computer Science. 4-7 years experience in ASIC design flow usage & development. RTL2GDS experience on advanced technology nodes (7nm and below). Experience with low power implementation and signoff, power gating, multiple voltage rails, UPF knowledge. Experience with multi-clock and multi-power domain designs. Proficiency with ECO implementation for timing, functional and DFT modes. Experience in Block-level and Full-chip floor-planning and power grid planning. Experience in Block-level and Full-chip design implementation. Strong expertise in Python & TCL programming. In-depth experience working with EDA tools like Fusion Compiler, ICC2/Innovus, Primetime, Calibre. The candidate should have minimum 5 years of experience in Physical Design. - This position is based at our Bengaluru office. - A 15 years full time education is required. Show more Show less

Qualcomm India Private Limited is a leading technology innovator that is dedicated to pushing the boundaries of what's possible to enable next-generation experiences and drive digital transformation for a smarter, connected future. As a Hardware Engineer at Qualcomm, you will play a crucial role in planning, designing, optimizing, verifying, and testing electronic systems. This includes working on a wide range of systems such as yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop innovative solutions that meet performance requirements. To qualify for this role, you should possess a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 6 years of experience in Hardware Engineering or a related field. Alternatively, a Master's degree with 5+ years of relevant experience or a PhD with 4+ years of experience is also acceptable. Key responsibilities for this position include having 5 to 10 years of experience in static timing analysis, constraints, and other physical implementation aspects. A solid understanding of industry-standard tools such as PT, Tempus, GENUS, Innovus, and ICC is required. You should have the ability to address extreme critical timing bottleneck paths and prepare complex ECOs for timing convergence across a wide range of corners. Experience in deep submicron process technology nodes is highly preferred along with knowledge of high-performance and low-power implementation methods. The ideal candidate should be willing to optimize power, push PPA to the best possible extent, and have expertise in Perl and TCL language. Qualcomm is an equal opportunity employer that is committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please reach out to disability-accommodations@qualcomm.com or contact Qualcomm's toll-free number. The company expects its employees to adhere to all applicable policies and procedures, including security measures for protecting confidential information. Please note that Qualcomm's Careers Site is exclusively for individuals seeking job opportunities at Qualcomm. Staffing and recruiting agencies are not authorized to use the site for submissions, and any unsolicited profiles, applications, or resumes will not be accepted. For more information about this role, please contact Qualcomm Careers directly.,

Qualcomm India Private Limited is a leading technology innovator that drives digital transformation to create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems for cutting-edge products. Collaborating with cross-functional teams, you will develop solutions to meet performance requirements. Minimum Qualifications: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 6+ years of Hardware Engineering experience OR - Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 5+ years of Hardware Engineering experience OR - PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 4+ years of Hardware Engineering experience Responsibilities: - 5 to 10 years of experience in static timing analysis, constraints, and other physical implementation aspects - Proficiency in industry standard tools PT, Tempus, GENUS, Innovus, ICC, etc. - Expertise in solving extreme critical timing bottleneck paths and preparing complex ECOs for timing convergence - Knowledge of minimizing power consumption and experience in deep submicron process technology nodes - Understanding of high performance and low power implementation methods - Strong fundamentals and expertise in Perl, TCL language - Willingness to optimize power, performance, and area to the best possible extent Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodation during the application/hiring process, please contact disability-accommodations@qualcomm.com or Qualcomm's toll-free number. The company expects its employees to adhere to all applicable policies and procedures, including security and confidentiality requirements. Note to Staffing and Recruiting Agencies: Qualcomm's Careers Site is exclusively for individuals seeking job opportunities at Qualcomm. Staffing agencies and their represented individuals are not authorized to submit profiles, applications, or resumes through this site. Unsolicited submissions will not be considered, and Qualcomm does not accept resumes or applications from agencies. For more information about this role, please reach out to Qualcomm Careers.,

Working on benchmarks to displace competition implementation solutions. Working on developing and debugging RTL-GDS implementation methodologies and flows. Providing technical solutions by identifying the design and/or EDA tool issues and provide an appropriate solution for customers. Effectively translate the findings into requirements for R&D to improve both tool behavior with enhancements as adaptive long-term solutions. Involved in deployment of new technologies on latest EDAversions and enable customers to migrate to newer versions achieving best PPA. Coming up with a proactive understanding of customers pain point and coming up with innovative solutions to address the same. Closely interacting with Synopsys R&D team and product development team to develop future technologies. This role requires you to act as customers advocate while talking to inhouse R&D and be a product brand ambassador while engaging with customers. The candidate must have good exposure to methodology changes to achieve targeted PPA metrics for complex designs. At least 2 years of experience in Physical Implementation RTL-GDS. Experience in autonomously debugging and resolving synth & PnR implementation challenges. Proficiency in Synopsys implementation tools is an advantage. The individual must be self-motivated and dedicated with strong debugging skills. Requires proficiency in scripting (tcl / unix / perl). Excellent communication skills including the ability to interface with customers and business unit personnel are essential.

Working on latest Synopsys implementation technologies ( Machine Learning , Physical Synthesis , Multi Source CTS etc ) to solve complex PPA challenges faced by Synopsys customers. Working on benchmarks to displace competition implementation solutions Working with customers to develop and debug RTL-GDS implementation methodologies and flows. Providing technical solutions by identifying the design and/or EDA tool issues and provide appropriate solution for customers Effectively translate the findings into requirements for R&D to improve both tool behavior with enhancements as adaptive long-term solutions. Involved in deployment of new technologies on latest EDA versions and enable customers to migrate to newer versions achieving best PPA Coming up with proactive understanding of customers pain point and come up with innovative solutions to address the same. Closely interacting with Synopsys R&D team and product development team to develop future technologies This role requires you to act as customers advocate while talking to inhouse R&D, and be a product brand ambassador while engaging with customers. Requirements: At-least 10 years of experience in Physical Implementation RTL-GDS. Experience in unsupervised debugging and resolving synth & PnR implementation challenges. Candidate must have good exposure towards methodology changes to achieve targeted PPA metrics for complex designs. Proficiency in Synopsys implementation tools is an advantage The person must be self-motivated and dedicated with solid debug skills. Requires proficiency in scripting (tcl / unix / perl). Excellent communication skills including ability to interface with customers and business unit personnel are essential.

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. 8 to 12 years of experience in static timing analysis, constraints and other physical implementation aspects. Solid understanding industry standard tools PT, Tempus, GENUS, Innovus, ICC etc. Solid grip on STA fixing aspects to solve extreme critical timing bottleneck paths. Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs. Should be aware about the tricks for minimizing power. Experience in deep submicron process technology nodes is strongly preferred. Knowledge of high performance and low power implementation methods is preferred. Willing to push PPA to the best possible extent. Strong fundamentals. Expertise in Perl, TCL language