Design for Testability Engineer NTek Software Solutions

9.0 - 13.0 years

0 Lacs

karnataka

On-site

You should have a minimum of 9 to 13 years of relevant experience in Design for Testability (DFT). Your expertise should include knowledge of DFT architectures and methodologies such as Scan insertions, ATPG, MBIST, JTAG, etc. It is essential to be proficient in DFT tools and methodologies from Cadence, Synopsys, or Mentor tools. Additionally, you should have experience in scripting languages like Python, Perl, or TCL.,

Posted 3 weeks ago

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Design For Test Engineer (DFT) Silcosys Solutions

2.0 - 7.0 years

4 - 9 Lacs

bengaluru

Work from Office

As a DFT Engineer, you will be responsible for developing and implementing Design for Test methodologies for complex VLSI designs. You will ensure the testability and manufacturability of our products by working closely with design, verification, and physical design teams, while employing state-of-the-art techniques to optimize coverage, cost, and performance. Responsibilities: 1. Develop and implement DFT architectures and strategies for complex SoC designs. 2. Insert and verify DFT features such as scan chains, Built-In Self-Test (BIST) for memory and logic, and boundary scan (IEEE 1149.1/1149.6). 3. Perform ATPG (Automatic Test Pattern Generation) and analyze coverage metrics to ensure hi...

Posted 4 weeks ago

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Design For Test Engineer (DFT) Silcosys Solutions

2.0 - 7.0 years

4 - 9 Lacs

Bengaluru

Work from Office

Posted 3 months ago

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Design For Testability (DFT) Engineer BAY Area Technology Solutions

1.0 - 5.0 years

3 - 7 Lacs

Hyderabad, Bengaluru

Work from Office

As a DFT Engineer, you will be responsible for developing and implementing Design for Test methodologies for complex VLSI designs. You will ensure the testability and manufacturability of our products by working closely with design, verification, and physical design teams, Responsibilities: Develop and implement DFT architectures and strategies for complex SoC designs. Insert and verify DFT features such as scan chains, Built-In Self-Test (BIST) for memory and logic, and boundary scan (IEEE 1149.1/1149.6). Perform ATPG (Automatic Test Pattern Generation) and analyze coverage metrics to ensure high fault coverage. Collaborate with RTL designers to ensure seamless integration of DFT features i...

Posted 3 months ago

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