ASIC Digital Design, Sr Staff Engineer

Job Description

At minimum, a Bachelor s degree in engineering is required with 12+ years of digital design experience using Verilog. Strong background in RISC architectures required. Working experience in RISC microprocessor IP design, programming at assembly and C/C++ level, DSP skills, an understanding of multi-core architectures and development techniques are a plus. Experience with multi-site development is helpful. The successful candidate is expected to: Design embedded RISC microprocessor IP at architectural and RTL level Write High-level architecture and micro-architecture specifications of the design Optimize design for performance, speed, area and power, generate hardware benchmarks and analyze results Develop standalone Verilog testbenches to verify their module Debug design issues / bugs working closely with the verification team Maintain our current processor product line and their derivative products Develop and maintain project plans. Work closely with program managers Good written, oral and problem-solving skills desired along with good communication skills and inter-person skills Work with multi-site, multi-time zone, multi-cultural teams on various aspects of the product like design, implementation, physical design, verification