Accelerated Verification Lead

13 years

0 Lacs

Bangalore Urban, Karnataka, India

Posted:3 weeks ago| Platform: Linkedin logo

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Skills Required

verification ip prototyping simulation emulation strategies software design integration synopsys siemens scripting automation python tcl perl analysis data prototype verilog flow development ethernet power measurement

Work Mode

On-site

Job Type

Full Time

Job Description

Mirafra is hiring for Accelerated Verification Lead Job Description Results-driven and technically proficient Accelerated Verification Lead with over 13+ years ofexperience in SoC/IP functional verification, including more than 7 years focused on Accelerated verification on emulator, acceleration, and prototyping flows for automotive hardware designs. Proven expertise in leading cross-functional verification teams and developing reusable, accelerable UVM environments that seamlessly bridge simulation to emulation and post-silicon validation. Specialized in driving Verification and Validation (V&V) reuse strategies, enabling coverage continuity, testbench portability, and early software validation through hybrid verification frameworks. Deep experience in ISO 26262-compliant design verification, functional safety requirements, and integration of real-world automotive scenarios into pre-silicon validation. Proficient with Synopsys ZeBu, Siemens Veloce platforms, ensuring accelerated bring-up of SoCuse cases and reducing time-to-market. Adept in scripting and automation using Python, TCL, and Perl, with hands-on CI/CD, coverage analysis, and debug tools (SimVision, Verdi, Indago). Summary & Achievements• • Reduced post-silicon bug escapes through early software-driven validation in emulation environments. (Accelerated Verification)• • Cut SoC bring-up time by 50% by architecting a unified simulation-to-emulation testbench with reusable transactors. • • Spearheaded the Accelerated verification plan for a next-gen ADAS SoC including use cases like Start Up, BOOTROM, Complex data path , Negative tests• • Enabled 80% reuse of verification components across simulation, emulation, and prototype platforms through modular UVM design. • • Successfully led a AV verification team of engineers across DV, emulation Key Skills- Accelerated Verification: Synopsys Zebu, Siemens Veloce, Verification Methodologies: UVM, System Verilog, Accelerable UVM, C based V&V Reuse & Bridging: ** Simulation-to-Emulation Flow, Coverage Continuity, Transactor Development is desirable **Automotive Domain Knowledge: ** ISO 26262, Functional Safety, ADAS SoCs, CAN, LIN, Ethernet etc Power measurement with fsdb dump from Emulation environment. Regards Kalpana Bhatia TA-Lead -Mirafra kalpanabhatia@mirafra.com 9718012760 Show more Show less

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