1588 Tcl Jobs - Page 18

Qualcomm India Private Limited is a leading technology innovator that aims to enable next-generation experiences and drive digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems. This includes working on circuits, mechanical systems, Digital/Analog/RF/optical systems, test systems, FPGA, and/or DSP systems to launch cutting-edge products. Collaboration with cross-functional teams is essential to develop solutions that meet performance requirements. To be considered for this role, you should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field along with 4+ years of Hardware Engineering experience. Alternatively, a Master's degree with 3+ years of experience or a PhD with 2+ years of experience is also acceptable. The ideal candidate should possess strong analytical and technical skills, especially in ASIC design. Responsibilities for this position include participating in ASIC development projects, focusing on Place and Route Implementation, Timing Closure, Low Power, Power Analysis, and Physical Verification. You will be expected to create design experiments, conduct detailed PPA comparison analysis, collaborate with various teams for optimization, and develop Place & Route recipes for optimal PPA results. Qualifications required for this role include 6-15 years of experience in High-Performance core Place & Route and ASIC design Implementation. Preferred qualifications involve extensive experience in Place & Route with FC or Innovus, knowledge of complete ASIC flow with optimization techniques, proficiency in STA using Primetime and/or Tempus, and skills in Perl/Tcl, Python, C++, among others. Problem-solving abilities, experience with CPU micro-architecture, low power implementation techniques, and clock tree implementation techniques are also desired. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If accommodation is needed during the application/hiring process, individuals can contact Qualcomm for support. The company expects its employees to adhere to all applicable policies and procedures, including confidentiality requirements. Staffing and recruiting agencies are advised that only individuals seeking a job at Qualcomm should use the Careers Site. Unsolicited submissions from agencies will not be accepted. For more information about this role, interested individuals can contact Qualcomm Careers directly.,

Qualcomm India Private Limited is seeking a Hardware Engineer to plan, design, optimize, verify, and test electronic systems. In this role, you will work on cutting-edge technologies in areas such as Digital/Analog/RF/optical systems, FPGA, and DSP systems to develop world-class products. Collaboration with cross-functional teams is key to meeting performance requirements and creating innovative solutions. Candidates for this position should hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with at least 2 years of Hardware Engineering experience. Alternatively, a Master's degree with 1 year of relevant experience or a PhD in a related field is also acceptable. The Qualcomm Noida CPU team is specifically looking for individuals to contribute to the development of high-performance and power-optimized custom CPU cores. Responsibilities include handling the hardening of complex HMs from RTL to GDS, which involves tasks such as Synthesis, PNR, and Timing. Desired experience for this role includes 2-5 years of experience in Physical design and STA. Proficiency in industry-standard tools for physical implementation such as Genus, Innovus, FC, PT, Tempus, Voltas, and redhawk is required. Candidates should have a strong understanding of the design flow from floorplan to PRO, timing signoff, IR drop, and physical verification aspects. Experience in deep submicron process technology nodes and knowledge of high-performance and low-power implementation methods are preferred. Strong fundamentals and expertise in Perl and TCL language are also desired. Qualcomm offers a dynamic and inclusive work environment where employees have the opportunity to collaborate with some of the most talented engineers in the world. The company is committed to providing reasonable accommodations to support individuals with disabilities during the application/hiring process. Qualcomm expects all employees to adhere to applicable policies and procedures, including those related to the protection of confidential information. Please note that Qualcomm does not accept unsolicited resumes or applications from agencies, and individuals represented by an agency are not authorized to apply through the Qualcomm Careers Site. For more information about this role, please reach out to Qualcomm Careers directly.,

You are a skilled professional with expertise in design and validation, ready to join a dynamic and innovative team. Your background includes developing and validating FPGA-based solutions, with solid knowledge of PCIe, CXL, USB, and other protocols. You are enthusiastic about tackling daily technical challenges and possess qualities such as self-motivation, proactivity, responsiveness, persistence, and outstanding problem-solving skills. Your key responsibilities will involve developing and implementing comprehensive validation plans for various interface solutions, ensuring compliance with industry standards. You will design FPGA-based solutions to support Hardware Assisted Verification (HAV) and conduct thorough testing and validation to identify and resolve issues. Collaboration with design teams, documentation of validation processes, and clear reporting to stakeholders will be essential. Additionally, you will work closely with cross-functional teams to ensure seamless project execution and stay updated on industry trends and advancements in validation methodologies and tools. To qualify for this role, you should hold a Bachelors or Masters degree in Electronics, Electrical, or Computer Engineering (or a related field) with a minimum of 8 years of design and validation experience. Your expertise should include extensive knowledge of FPGA-based design and validation methodologies, a strong understanding of high-speed protocols like PCIe, CXL, and USB, and proficiency in programming languages such as C/C++, SystemVerilog, Verilog, Perl, Python, and TCL. Experience with emulation or prototyping platforms like ZeBu or HAPS would be advantageous. Your problem-solving skills, attention to detail, communication, and collaboration abilities are crucial for effective teamwork and project success.,

Qualcomm India Private Limited is a company of inventors at the forefront of 5G technology, unlocking new possibilities that will revolutionize industries, create job opportunities, and enhance lives. As part of the Engineering Group in the Hardware Engineering division, you will be joining a dynamic team responsible for designing Low Power controller IP cores and subsystem digital design for cutting-edge Snapdragon SoCs used in mobile, compute, IoT, and Automotive markets globally. In this role based at Qualcomm's Bangalore office, your key responsibilities will include micro-architecture and RTL design for Cores/subsystems, collaborating closely with Systems, Verification, SoC, SW, PD & DFT teams, enabling software teams to utilize hardware blocks, qualifying designs through static tool checks, and reporting progress status against expectations. Preferred qualifications for this position include 5 to 10 years of experience in digital front-end design (RTL design) for ASICs, expertise in RTL coding in Verilog/SV/VHDL, familiarity with UPF and power domain crossing, experience in synthesis, logical equivalence checks, RTL and netlist CLP, proficiency in various bus protocols, low power design methodology, clock domain crossing designs, formal verification, and database management flows. Additionally, expertise in Perl/TCL/Python language, post-Si debug, and strong communication skills are valued qualities for this role. To be considered for this opportunity, you should hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with at least 4+ years of Hardware Engineering experience, or a Master's degree with 3+ years of relevant work experience, or a PhD with 2+ years of related work experience. Qualcomm is an equal opportunity employer committed to providing accessible accommodations for individuals with disabilities during the application/hiring process. Please reach out to disability-accommodations@qualcomm.com for support. The company expects its employees to comply with all applicable policies and procedures, including confidentiality requirements. If you are a staffing or recruiting agency, please note that Qualcomm's Careers Site is exclusively for individual job seekers, and submissions from agencies will be considered unsolicited. For more information about this role, please contact Qualcomm Careers directly.,

You should possess in-depth knowledge and hands-on experience in Netlist2GDSII Implementation, including tasks such as Floorplanning, Power Grid Design, Placement, Clock Tree Synthesis (CTS), Routing, Static Timing Analysis (STA), Power Integrity Analysis, Physical Verification, and Chip finishing. It is essential to have experience with Physical Design Methodologies and sub-micron technology, particularly in 16nm and lower technology nodes. Moreover, you should have expertise in Analog and Mixed Signal Design and be familiar with handling designs with more than 5M instance count and operating at a frequency of 1.5GHz. Proficiency in programming languages such as Tcl, Tk, and Perl is required to automate the design process and enhance efficiency. Hands-on experience with PnR Suite from Cadence & Synopsys, specifically Innovus & ICC2, is a must. Additionally, you should have a strong background in Static Timing Analysis using tools like PrimeTime for SI analysis, EM/IR-Drop analysis with PT-PX and Redhawk, as well as Physical Verification using Calibre. Understanding the practical application of methodologies, Physical Design Tools, Flow Automation, and driving improvements in these areas is highly beneficial. Experience in complex SOC integration, Low Power and High-Speed Design, as well as proficiency in Advanced Physical Verification Techniques, are desirable skills for this role.,

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary We know our employees’ ideas change the world. For more than three decades, we’ve been a global leader in mobile technology, continually pushing the boundaries of what’s possible. Working with customers across industries — from automotive to health care, from smart cities to robotics— we continue to accelerate innovation and unlock new possibilities in a time where everything is connected. By joining the Qualcomm family, you too can bring the future forward faster. Qualcomm is looking for an energetic, creative and self-driven engineer to work in Modem , Multimedia , Connectivity , Computer Vision and Image Processing , software implementation and hardware acceleration. The work will directly influence the various subsystems within the SoC. The ideal candidate would have very strong problem solving and analytical skills combined with creativity and a passion for innovation. They would be able to carry forward that new idea, concept, and/or application that will propel systems to new levels of effectiveness and efficiency. At Qualcomm you will perform detailed technical analysis, translate ideas into models, SW and/or HW and work closely with other teams to help deliver real products. At Qualcomm, the sky's the limit. College Graduates play important roles everywhere in the company. Many of our 27,000+ employees join us right out of school because we're working on the cutting edge in wireless. Complex wireless devices are only as powerful as the software that runs them. As a software engineer, you will develop, implement and maintain multimedia, gaming and application software for the world's leading-edge mobile devices. We know our employees’ ideas change the world. For more than three decades, we’ve been a global leader in mobile technology, continually pushing the boundaries of what’s possible. Working with customers across industries — from automotive to health care, from smart cities to robotics— we continue to accelerate innovation and unlock new possibilities in a time where everything is connected. By joining the Qualcomm family, you too can bring the future forward faster. SOC & Hard Macro Physical Design SOC Validation & Debug RF & Analog Layout RF/Analog/Mixed Signal/Power IC Design Low Power Design Board and FPGA Design\ Digital ASIC Design Design/SOC Verification CAD Solution Engineer Design for Test (DFT) CPU Design Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Educational Background Masters, Bachelors: Electrical Engineering , VLSI , Embedded and VLSI , ECE Must have educational background in one or more of the following areas: Verifying SoC with embedded RISC/DSP processors, communications/ networking ASICs. Verilog or VHDL, C/C++, Tcl/Perl/shell-scripting. RTL design experience and/or strong OO programming knowledge Knowledge of wireless/wired communications and protocols or graphics/video multi-media is a plus. Knowledge in PLL, LNA, OpAmp, CMOS, ADC/DAC, Cadence, SpectreRF, or Layout is required in RF/Analog/Mixed Signal IC Design. Excellent analytical and problem solving skills. Ability to collaborate and work in teams. Good verbal and written communication skill Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3078320

About Us: At Dabster, we specialize in connecting top talent with leading global companies. We are currently seeking a " Design Verification Engineer " to join one of our key clients on a Fixed term tract with strong potential for extension. Our mission is to be the foremost recruitment specialist in securing exceptional talent for a diverse range of global clients. This is a UK/EU-based role, and visa sponsorship will be provided for eligible candidates. Who Will You Work With: A leading semiconductor and software design company specializing in energy-efficient microprocessor architectures. Its processor designs power the vast majority of smartphones, tablets, embedded systems, and IoT devices worldwide. By licensing its technology to global tech giants, the company plays a pivotal role in the modern computing and electronics ecosystem. About the Role: As a Design Verification Engineer , you should be expertise in SystemVerilog and UVM to develop and execute comprehensive verification plans, build UVM testbenches, and perform block to SoC-level verification. Proficiency in simulation tools, scripting for automation, and advanced debug techniques is essential. Key Responsibilities: Define and execute comprehensive verification plans based on design specifications and architecture. Develop and maintain UVM-based testbenches and environments. Write, simulate, and debug testcases using SystemVerilog. Perform block-level and subsystem-level verification, ensuring alignment with functional and performance targets. Run regression tests, analyse coverage reports, and identify design bugs. Collaborate with RTL designers, integration engineers, and system architects to ensure high-quality deliverables. Support gate-level simulations, formal verification, and other advanced verification methodologies. Preferred Skills: Proven experience with SystemVerilog and UVM methodology. Strong understanding of digital design concepts and verification principles. Experience with tools such as Synopsys VCS, Cadence Xcelium , or Mentor Questa . Familiarity with scripting languages like Python, Perl, or Tcl for automation. Solid grasp of coverage-driven verification and assertion-based verification techniques. Experience with regression management , debug tools like Verdi , and waveform analysis . Exposure to IP/subsystem/SoC-level verification is a plus. What We Offer: Contract Type: 6-months contract with possible extension Remote Flexibility: Fully remote Collaborative Environment: Work closely with industry-leading teams and contribute to cutting-edge projects. This is a UK/EU-based role, and visa sponsorship will be provided for eligible candidates. How to apply: Please submit your CV with relevant experience via LinkedIn Easy Apply or directly to Sushma.gungi@dabster.net. Interview Process: The process typically includes one or two rounds of technical interviews followed by a business alignment discussion.

We Are: Drive technology innovations that shape the way we live and connect. Our technology drives the Era of Pervasive Intelligence, where smart tech and AI are seamlessly woven into daily life. From self-driving cars and health-monitoring smartwatches to renewable energy systems that efficiently distribute clean power, Synopsys creates high-performance silicon chips that help build a healthier, safer, and more sustainable world. Apprenticeship Experience: At Synopsys, apprentices dive into real-world projects, gaining hands-on experience while collaborating with our passionate teams worldwide—and having fun in the process! You'll have the freedom to share your ideas, unleash your creativity, and explore your interests. This is your opportunity to bring your solutions to life and work with cutting-edge technology that shapes not only the future of innovation but also your own career path. Join us and start shaping your future today! Mission Statement: Our mission is to fuel today's innovations and spark tomorrow's creativity. Together, we embrace a growth mindset, empower one another, and collaborate to achieve our shared goals. Every day, we live by our values of Integrity, Excellence, Leadership, and Passion, fostering an inclusive culture where everyone can thrive—both at work and beyond. What You’ll Be Doing: Developing simulation models and platforms in SystemC for early software development and validation. Providing technical support to customers and participating in the development of flows and methodologies in Synopsys’ Virtualizer tools. Working directly with leading customers in the areas of AI, Automobile, Cloud, Networking, etc. Maintain the Jenkins and nightly test flows for VDK quality assesment and management. What You’ll Need: Graduate in BE/BTech or equivalent in Computer Science, Electrical or Electronics Engineering, or related fields. Proficiency in C/C++. Knowledge of Linux environment and scripting in Shell, Tcl, Python. Knowledge of computer architecture. Understanding of SystemC and TLM (Preferred). Knowledge of Embedded Software design (Preferred). Strong written and verbal communication skills. Strong problem-solving abilities. Good interpersonal skills. Key Program Facts: Program Length: 12 months Location: Noida, India Working Model: Onsite Full-Time/Part-Time: Full-time Start Date: August/ September 2025 Equal Opportunity Statement: Synopsys is committed to creating an inclusive workplace and is an equal opportunity employer. We welcome all qualified applicants to apply, regardless of age, color, family or medical leave, gender identity or expression, marital status, disability, race and ethnicity, religion, sexual orientation, or any other characteristic protected by local laws. If you need assistance or a reasonable accommodation during the application process, please reach out to us.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are passionate about solving complex problems at the intersection of software engineering and semiconductor technology. Your curiosity drives you to explore new solutions and approaches, especially in high-impact areas such as memory characterization and automation. With a strong foundation in computer science, electronics, or a related discipline, you thrive in environments where collaboration, innovation, and technical excellence are valued. You are detail-oriented, analytical, and always eager to learn and adapt as technology evolves. You take pride in building robust, maintainable code and are committed to delivering quality solutions that make a tangible difference. As a team player, you communicate clearly, seek feedback, and contribute to a culture of openness and continuous improvement. Whether working independently or in cross-functional teams, you bring a sense of accountability and ownership to your work. You are excited by the prospect of impacting the next generation of semiconductor products and motivated by the opportunity to drive productivity and efficiency through automation. If you are ready to challenge yourself, innovate, and help shape the future of memory IP development, Synopsys is the place for you. What You’ll Be Doing: Designing and developing robust software tools for automating memory characterization workflows, including simulation setup, data extraction, and report generation. Collaborating closely with memory design, CAD, and validation teams to understand requirements and implement solutions that enhance accuracy, scalability, and performance of characterization flows. Integrating EDA tools such as SPICE simulators, Liberty format analyzers, and waveform viewers into advanced automation flows. Optimizing simulation execution on large compute clusters and efficiently managing the vast data sets generated during memory characterization. Building modular, maintainable, and high-performance codebases using C++, Python, Shell/TCL scripts, and industry-standard software engineering tools. Contributing to the development of test infrastructure, debugging tools, and validation methodologies to ensure the correctness and consistency of characterization results. Participating in code reviews, providing innovative ideas, and driving improvements in productivity and tool efficiency across the team. The Impact You Will Have: Accelerate the delivery of high-performance memory compilers for advanced technology nodes (e.g.,5nm,3nm, and beyond), enabling cutting-edge products. Streamline and automate engineering flows, reducing manual effort and enhancing productivity for multidisciplinary teams. Enhance the quality and reliability of characterization data, directly contributing to Process Design Kits (PDKs), EDA tools, and customer deliverables. Drive innovations that improve cost-efficiency, scalability, and competitiveness of Synopsys’ global IP portfolio. Contribute to the continuous improvement of internal infrastructure, processes, and best practices, fostering a culture of technical excellence. Empower internal and external customers through robust, user-friendly tools that enable faster, more reliable delivery of semiconductor solutions. What You’ll Need: B.Tech/MTech in Computer Science, Electronics, or a related field. At least 2 years of experience in software development or EDA tool development, preferably within the semiconductor industry. Proficiency in C/C++, TCL, Python, SQL, and scripting languages such as Shell. Experience with debugging tools such as GDB, and memory debugging tools like Valgrind or Purify. Strong understanding of machine learning algorithms (supervised, unsupervised, reinforcement learning). Hands-on experience with Python ML libraries such as scikit-learn, TensorFlow, or PyTorch. Who You Are: Detail-oriented with excellent analytical and problem-solving abilities. Possess strong verbal and written communication skills, able to articulate complex technical concepts clearly. A collaborative team player who thrives in cross-functional and multicultural environments. Demonstrates accountability and ownership in delivering high-quality work. An innovative thinker passionate about technology, automation, and continuous learning. The Team You’ll Be A Part Of: You’ll be joining a dynamic and forward-thinking team dedicated to developing and maintaining advanced memory characterization tools for next-generation semiconductor technologies. The team is known for its strong collaboration across domains such as software, CAD, and design, and for fostering a culture of inclusivity and openness. Committed to continuous improvement, the team values innovation and feedback while delivering high-quality, impactful solutions that empower both internal teams and external customers. Together, you will be driving the future of memory IP development by solving complex challenges and pushing the boundaries of performance, scalability, and automation. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Dassault Systemes 3DEXPERIENCE DELMIA Customization Good to have skills : NAMinimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your typical day will involve collaborating with various teams to ensure that application requirements are met, overseeing the development process, and providing guidance to team members. You will also engage in problem-solving activities, ensuring that the applications are aligned with business objectives and user needs, while fostering a collaborative environment that encourages innovation and efficiency. Roles & Responsibilities:1. Experience on EKL Business logics, know how apps, data setup etc2. Experience on 3DX Platform customization using CAA.3. Exposure to 3DEXPERIENCE webservices is plus.4.Capable of understanding and contributing to the technical solution from 3DEXPERIENCE design through code level.5.Capable of providing solutions & mentoring support to the team.6.Taking ownership of individual tasks(implementation and bug fixing) and ensuring the delivery of assignments on-time with quality. Extending Support to the team when required7.Awareness and adherence to the best practices to the coding standards of Enovia API/EKL/CAA.8. Experience on DevOps tools like Jenkins/Git/Jira. Professional & Technical Skills: - 1.Experience in 3DExperience Catia/Enovia customization, configuration and SME role.2. Excellent verbal and written communication skills in English.3. Should be a team player. Additional Information:- The candidate should have minimum 6+ years of experience in 3DExperience/Catia/Enovia - Customization.- This position is based at our Bengaluru office.- A 15 year full time education is required. Qualification 15 years full time education

Job Description The candidate will be responsible for implementing the place and route of design blocks including floorplanning, placement, clock tree building, routing, timing optimizations, DRC, LVS fixing, IR drop analysis, Formal verification, power intent checks etc. The candidate will also be responsible for block-level physical design closure in terms of timing, power, DRC/LVS, etc. Requirements 3-8years of experience in ASIC Physical Design Have good knowledge of the entire physical design process from floorplan to GDSII generation Good Exposure to Physical Verification Process Have hands-on experience in the latest sub-micron technologies below 10 nm Hands–on experience in leading PnR tools Synopsys ICC/ICC2 Experience in low power designs and handling congestion or timing critical tiles will be preferred Should be a quick learner and have good attention to detail Experience in ECO implementation preferred Scripting skills in Perl/Tcl/Python etc Must have good communication & problem-solving skills. Should be able to handle PnR tasks with minimal supervision

Applications are invited from interested and motivated candidates for the Post of Junior Research Fellow ( JRF ) in a time bound research project for a temporary period, purely on contractual basis as per the following details: for CSIR Funded Project in the Centre For Functional Materials (CFM), at Vellore Institute of Technology (VIT), (25WS(016)/2023-24/EMR-II/ Aspire dated 16-04-2024) Position : Junior Research Fellow No. of Vacancies : 01 (ONE) Title of the Project : “Fabrication of magneto ceramic MEMS devices using 3D printing”. Department : Centre for Functional Materials Project Tenure : 3 Years Job Description : The selected candidate is expected to perform research activities with goals in line with the aforementioned project and publish the results Essential Qualification : The minimum qualifications are BS 4 years programme/Integrated BS-MS/MSc/BE/BTech or equivalent degree, with 55% marks and passing of NET/GATE test. The selection for award of JRF is made on the basis of a competitive written test organized jointly by CSIR and UGC at National Level. Age Limit : 28 years Age Relaxation : The upper age limit is relaxable up to 5 years in the case of candidates belonging to schedule castes / tribes/ OBC, women and physically handicapped candidates. Stipend : Rs. 31,000/- per month + HRA (as per the Institution rules) Sponsoring Agency : CSIR, Delhi. Principal Investigator : Dr. Madhuri W Professor and Director Centre for Functional Materials Vellore Institute of Technology (VIT) Vellore - 632 014, Tamil Nadu. Co-Principal Investigator : - - Send your resume along with relevant documents pertaining to the details of qualifications, scientific accomplishments, experience (if any) and latest passport size photo etc. on or before ( 28/07/2025) through online http://careers.vit.ac.in No TA and DA will be paid for appearing the interview. Shortlisted candidates will be called for an interview at a later date which will be intimated by email. The selected candidate will be expected to join immediately.

Apply now » Senior Technical Lead Company: NEC Corporation India Private Limited Employment Type Office Location: Kandanchavadi, Perungudi, TN, IN, 600096 Work Location: Hybrid Req ID: 4517 Description Reporting Relationship: Reporting to Project Manager Job Summary NEC Corporation India Pvt. Ltd is looking for an experienced and highly talented FPGA Lead with strong telecom and Aerospace expertise at NEC Mobile Network Excellence Center (NMEC), Chennai Scope of work Implementing FPGA code on the target hardware & testing with other system components and software RTL Design, Implementation, Testing, Integration and delivery of FPGA based hardware systems for Telecom and Aerospace Applications Interaction with various vendors/ OEMs to identify the right solution Co-work with internal/external engineering team on Hardware, RF, Mechanical and Software team etc. Involve in R&D activities demonstrating Proof of Concept in various technologies for aerospace/ defence related design techniques. Qualifications BE/B.Tech/M.E/M.Tech Or Its Equivalent Experience 8+ years Domain Skills Expert in FPGA flows with Xilinx, including compilation, synthesis, debug, performance and implementation of advanced features Good Hands on Linting, Static Timing Analysis, Equivalence Checking & Clock Domain Crossing. Experience in developing verification environment to verify developed items using self-checking test benches, BFMs, checkers/Monitors & Score boards using VHDL/verilog. Prior experience in integrating Nios, MPIS, MicroBlaze, ARM Cortex, etc. GTX / GTH transceivers & 10GE MAC / DMA controller / PCIe Gen3 / CPRI / JESD / FFT IP core Common control interfaces design, like AMBA AXI, UART, SPI, I2C, DDR, Ethernet, USB, etc.. Knowledge on programming languages such as Verilog, VHDL and system Verilog Experience with any scripting language for automation (Perl/TCL/Python). Familiar with standard FPGA HW bring-up activities and testing Experience with HW measuring tools like oscilloscopes, Signal analysers, JTAG Emulators Specialization Description Responsible for improving or developing new products, components, equipment, systems, technologies, or processes including: Ensuring that research and design methodologies meet established scientific and engineering standards Assisting with formulating business plans and budgets for product development Analyzing quality/safety test results to ensure compliance with internal and external standards Keeping abreast of new developments in the industry and translating those developments into new and viable options for the organization and customers Organizing technical presentations to customers and/or industry groups Monitoring product development outcomes to ensure technical, functional, cost, and timing targets are met In some organizations, may be responsible for managing product regulatory approval process Level Description Experienced level professional that applies practical knowledge of job area typically obtained through advanced education and work experience. Works independently with general supervision. Works to achieve operational targets within the job area with a direct impact on function / sub-function results. Problems faced are difficult but typically not complex. May influence others within the job area through explanation of facts, policies and practices. Headquartered in Japan, NEC is a leader in the integration of IT and network technologies. With over 123 years of expertise in providing solutions for empowering people, businesses, and society, NEC stands tall as a champion in enabling change and transformation across the globe. Present in India since 1950, NEC has been instrumental in burgeoning India’s digitization journey continually for the past 70 years. NEC India has proved its commitment to orchestrating a bright future through its diverse businesses from Telecommunications to Public Safety, Logistics, Transportation, Retail, Finance, Unified Communication and IT platforms , serving across the public and private sectors. NEC India, through the deployment of cutting-edge technology, has been powering India in seminal ways, making lives easier, safer, and more productive for all. With its Centre of Excellence for verticals like Analytics platform solutions, Big Data, Biometrics, Mobile and Retail , NEC India brings to the table, innovative, seamless solutions for India and across the world. NEC India is headquartered in New Delhi and has its offices panned across the country. It has branches in Ahmedabad, Bengaluru, Chennai, Mumbai, Noida and Surat. Specialties IT & Networking Solutions, Unified Communication Solutions, Safety and Security Solutions, Integrated Retail Solutions, Data Centre Solutions, Safe and Smart City Solutions, Transportation Solutions, SDN Solutions, Carrier Telecom Solutions, and Solutions for Society. NEC Career Site - LinkedIn Apply now »

Alternate Job Titles: Staff Implementation Engineer Senior Physical Design Engineer Technical Solutions Engineer We Are: At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you. Our Silicon Design & Verification business is all about building high-performance silicon chips—faster. We’re the world’s leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost, and performance—eliminating months off their project schedules. You Are: You are a highly skilled and passionate engineer with a talent for tackling complex problems and a strong desire to advance cutting-edge technology. With over five years of experience in Physical Implementation RTL-GDS, you bring deep expertise in autonomously diagnosing and resolving synthesis and place-and-route (PnR) challenges. You are proficient in scripting languages like Tcl, Unix, and Perl, and possess an in-depth knowledge of Synopsys implementation tools. Your strong communication abilities enable you to engage effectively with both customers and internal teams, ensuring precise and attentive fulfillment of their needs. Driven, self-starting, and highly collaborative, you excel in environments where you can advocate for customers and represent the product. Additionally, your ability to translate technical insights into actionable requirements for R&D teams plays a crucial role in driving innovation and strengthening Synopsys solution capabilities. What You’ll Be Doing: Providing technical support and expertise to global customers using Synopsys Implementation products. Engaging in specific flagship projects and providing enabling solutions in all parts of the design implementation flow. Participating in technical campaigns to drive Synopsys solution adoption through hands-on involvement. Acting as a customer advocate while interfacing with the product development team to influence product roadmap and future technologies. Contributing to technical articles in the Knowledge Base to provide self-help guidance for common customer issues. Rolling out new product methodologies by providing training and technical support to customers. The Impact You Will Have: Delivering comprehensive support and effective technical solutions to enhance customer satisfaction. Driving innovation by addressing design challenges and improving product performance based on customer feedback. Collaborating with R&D teams to advance future technologies and product features. Promoting Synopsys tools to grow market presence and adoption. Ensuring seamless EDA transitions to optimize customer outcomes. Strengthening Synopsys' reputation as a leader in silicon design and verification. What You’ll Need: Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field. Expertise in Implementation Methodologies and Synopsys Tool Fusion Compiler. Knowledge of STA, Low Power Flows, Design Planning, and scripting languages like TCL/Python. Thorough understanding of RTL to GDS flows and methodologies. Excellent verbal and written communication skills. Experience in customer-facing roles is a plus. Deep domain knowledge in Synthesis, Place & Route, and timing analysis, with multiple chip tape-outs at 7nm or lower nodes. Who You Are: An effective communicator with strong interpersonal skills. A proactive self-starter who takes initiative and drives projects to completion. A collaborative team player who values teamwork and collective success. Detail-oriented and committed to delivering high-quality solutions. Adaptable and eager to learn new technologies and methodologies. The Team You’ll Be A Part Of: You will be part of a dedicated team of application engineers focused on providing top-notch technical support and solutions to our customers. The team's core purpose is to ensure customer success and satisfaction by leveraging Synopsys' cutting-edge technologies and products. You will collaborate closely with other engineers, sales teams, and product development teams to achieve our collective goals and drive innovation in the industry. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Category Engineering Hire Type Employee Job ID 12216 Remote Eligible No Date Posted 14/07/2025 Alternate Job Titles: Senior R&D Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and driven engineering professional with a strong foundation in VLSI concepts, CMOS circuit design, and EDA tools. With2-3 years of hands-on experience in the semiconductor industry, you thrive in dynamic environments where innovation, collaboration, and continuous learning are valued. Your curiosity drives you to explore emerging technologies such as AI/ML, and you have developed proficiency in scripting languages like TCL and Python to solve complex engineering challenges. You have a keen eye for detail and a solid grasp of timing, power, and noise analysis, enabling you to deliver robust and reliable design solutions. Your exposure to industry-standard tools such as VCS, Design Compiler, Primetime, and HSPICE/Primesim has honed your technical expertise, and you are comfortable navigating various stages of the design flow, from synthesis to signoff. As a team player, you communicate effectively,

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: SILICON DESIGN ENGINEER 2 THE ROLE: Play a critical role in shaping the next generation of AMD products, including CPUs, GPUs, and adaptive compute engines. Interface with large, globally distributed design teams to support complex and collaborative development efforts. Drive automation of Synthesis, Place and Route, Logic Eqv, Functional ECO methodologies targeting advanced technology nodes. Own the development and support of next-generation synthesis flows, ensuring scalability and efficiency across projects. Collaborate closely with EDA vendors to identify innovative solutions, resolve tool/methodology issues, and enhance flow capabilities. Contribute to the evolution of AMD’s design infrastructure by improving automation, performance, and methodology robustness. KEY RESPONSIBILITIES: Responsible for developing and automating Synthesize, PnR and Functional ECO, for various designs at advanced technology nodes. Script out utilities to automate different components of the implementation flow. Support design teams across global sites on various issues related to Front-End Synthesis flow targets. CAD flow and methodology development on advanced process nodes are preferred. Tool Expertise Required: Hands on experience in Front-End Synthesis, Logical Eqv and Conformal ECO flows. Hands on experience in industry standard tools such as DC, Fusion Compiler, FM,VCLP, ICC2, Innovus, Conformal. Hands on experience in any of PnR, STA, Formal Verification or RTL coding domains is a plus. CAD and automation mindset ACADEMIC CREDENTIALS: Masters degree in Electronics Engineering 3-6 years of experience in CAD flow and methodology development on advanced nodes. Proficiency in one or more scripting languages namely Python, Tcl, Perl, sed/awk Strong problem-solving skills and analytical thinking Team player, good work ethic, and excellent communication skills. Job Location : Hyderabad #LI-SR4 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: AECG ASIC DFX - SMTS SILICON DESIGN ENGINEER T HE ROLE : AECG SSD ASIC is a centralized ASIC design group within AMD’s Adaptive and Embedded Computing Organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products. As a member of the AECG SSD ASIC Group, you will help bring to life cutting-edge designs. As a member of the DFT design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. K EY RESPONSIBLITIES : Implementation and verification of DFT architecture and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning Working with a multi-functional and cross-GEOs team of engineers on DFT (design-for-test) and DFD (design-for-debug) architecture and methodology. Performing design-for-test (DFT) RTL design using architectural specifications and design generation flows Performing DFT RTL integration, synthesis, equivalency checking, timing analysis and defining constraints, verification of DFx logic at RTL and GLS. Writing and maintain DFT documentation and specifications. Developing CAD software, scripts and other support technology to enable successful construction of DFT logics in complex SoC design. Performing scan insertion, ATPG verification and test pattern generation Providing DFT feature bring-up and pattern debug support to production engineering team during first silicon bring-up, qualification and failure analysis. P REFERRED EXPERIENCE : Minimum 12 years of DFT design, integration, verification, ATPG and Silicon Debug experience. Demonstrated technical leadership and works well with cross-functional teams. Excellent communication and interpersonal skills Understanding of Design for Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc.) Experience in complex ASIC design (multi-million gates) in DFT/DFD techniques such as JTAG/IEEE standards, scan and ATPG, on-chip test pattern compression and at-speed testing using PLL, memory BIST and repair, logic BIST, power-gating, on-chip debug logic, testing of high speed SerDes IO and analog design. Understanding various technologies that must work with DFT/DFD technology such as CPU’s, memory and I/O controllers, etc. Expertise in scan compression architecture, scan insertion and ATPG methodologies are essential. Working knowledge and experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations Experience in solving logic design or timing issues with integration, synthesis and PD teams. Good working knowledge of UNIX/Linux and scripting languages (e.g., TCL, c-shell, Perl), C++ programming Knowledge in EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis. Knowledge of ATE and digital IC manufacturing test is a plus. Strong problem-solving skills. Team player with strong communication skills. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-RP1 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Job responsibilities: Develop test plans, tests and verification infrastructure for a complex IP/Sub-System or lead major deliverables for SoC Create verification environment using UVM methodology Hands on in end to end Logic Verification Process including Verification Planning, Functional Coverage planning and development, Test case development, regression, debug and Coverage closure Create reusable bus functional models, monitors, checkers and scoreboards Drive functional coverage driven verification closure. Work with architects, designers, and post-silicon teams Hands-on contributions to SVA development like coding, porting and maintaining System Verilog Assertions including Formal Verification Development of tools for Design and Verification support Debug failures and root-cause it by interacting with other teams/groups Etc. Qualifications 3-8 Years of relevant experience - Education: B.E/B.Tech/M.Tech in ECE/VLSI/Electrical Engineering Skills Required/Preferred Software Skills Required: Proficiency in Computer Science fundamentals – object oriented design, data structures, algorithms, design, problem solving, and complexity analysis Basic knowledge of with c, c++, SystemC, perl, python, tcl, shell is preferable - Functional Verification: Unit/Sub-system/SOC level verification experience Experience in leading verification closure of complex IP/SOC for at least one project Exposure to industry standard verification tools for simulation and debug RTL & Gate Level Simulations Proficiency in Verilog, System Verilog , Assertions and UVM Exposure to Verification Fundamentals Verification Automation using scripts like Python, Perl,shell,tcl/tk Good debugging and problem solving skills. Good communication skills and ability, desire to work as a team player Exposure to Analog verification will additional plus point -Digital design Concepts CMOS VLSI, Digital Circuits Knowledge on Memory (preferred) (SRAM/DRAM/ROM/ Flash ) Circuits/Logic Preferred exposure NCSIM, Xcellium, IMC, IEV, Verdi, Jaspergold, VS Formal Cadence Schematic and layout environment Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at jobs.accommodations@sandisk.com to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Job responsibilities: Develop test plans, tests and verification infrastructure for a complex IP/Sub-System or lead major deliverables for SoC Create verification environment using UVM methodology Hands on in end to end Logic Verification Process including Verification Planning, Functional Coverage planning and development, Test case development, regression, debug and Coverage closure Create reusable bus functional models, monitors, checkers and scoreboards Drive functional coverage driven verification closure. Work with architects, designers, and post-silicon teams Hands-on contributions to SVA development like coding, porting and maintaining System Verilog Assertions including Formal Verification Development of tools for Design and Verification support Debug failures and root-cause it by interacting with other teams/groups Etc. Qualifications 3-8 Years of relevant experience Education: B.E/B.Tech/M.Tech in ECE/VLSI/Electrical Engineering Skills Required/Preferred (SRAM/DRAM/ROM/ Flash ) Circuits/Logic Software Skills Required: Proficiency in Computer Science fundamentals – object oriented design, data structures, algorithms, design, problem solving, and complexity analysis Basic knowledge of with c, c++, SystemC, perl, python, tcl, shell is preferable Functional Verification: Unit/Sub-system/SOC level verification experience Experience in leading verification closure of complex IP/SOC for at least one project Exposure to industry standard verification tools for simulation and debug RTL & Gate Level Simulations Proficiency in Verilog, System Verilog , Assertions and UVM Exposure to Verification Fundamentals Verification Automation using scripts like Python, Perl,shell,tcl/tk Good debugging and problem solving skills. Good communication skills and ability, desire to work as a team player Exposure to Analog verification will additional plus point -Digital design Concepts CMOS VLSI, Digital Circuits Knowledge on Memory (preferred) Preferred exposure NCSIM, Xcellium, IMC, IEV, Verdi, Jaspergold, VS Formal Cadence Schematic and layout environment Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at jobs.accommodations@sandisk.com to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.

Job Description We are seeking a talented and detail-oriented Physical Backend Design Engineer to join our IC (Integrated circuit) development team. The role involves key aspects of physical design, including automated place and route, floorplanning, clock tree synthesis (CTS), static timing analysis (STA), power analysis, and physical verification (DRC/LVS). The ideal candidate will have a strong knowledge of physical design methodologies, experience with industry-standard tools, and a passion for delivering high-quality semiconductor solutions. How You Will Contribute And What You Will Learn Perform floorplanning, partitioning, and optimization to achieve area, power, and performance targets. Execute automated place and route (PnR) using industry-standard tools to generate physical layouts. Implement clock tree synthesis (CTS), ensuring low skew and efficient clock distribution. Conduct static timing analysis (STA) to verify timing closure and ensure the design meets performance requirements. Perform power analysis, including IR drop and electromigration (EM) checks, to optimize power distribution networks. Conduct physical verification tasks, including design rule checks (DRC) and layout vs. schematic (LVS) checks, to ensure manufacturability and compliance with foundry standards. Collaborate with design, verification, and DFT teams to resolve physical design challenges and improve chip performance. Work closely with foundry teams to address process technology issues and implement best practices. Key Skills And Experience You have: Bachelor’s Degree in Electrical Engineering, Computer Engineering, or a related field (Master’s preferred) 3+ years of experience in physical backend design for ICs. Complex chip designs through all stages of physical implementation Experience with tape-out of designs for advanced nodes is highly desirable Strong knowledge of physical design concepts, including place and route (PnR), clock tree synthesis (CTS), static timing analysis (STA) and power grid design Experience with physical verification tools like Cadence Pegasus or Mentor Calibre Familiarity with parasitic extraction tools (e.g., StarRC, Quantus, Calibre xRC) Scripting skills in Python, Tcl, Perl, or Shell for automation Required Tools: Cadence Innovus, Cadence Quantus, Cadence Tempus, Cadence Pegasus suite It would be nice if you also had: Experience with advanced process nodes (e.g., 7nm and below) Knowledge of low-power design techniques, such as multi-Vt, multi-Vdd, or clock gating Familiarity with DFT concepts and tools, Chip packaging and thermal analysis considerations, FinFET technology and 3D IC design methodologies About Us Come create the technology that helps the world act together Nokia is committed to innovation and technology leadership across mobile, fixed and cloud networks. Your career here will have a positive impact on people’s lives and will help us build the capabilities needed for a more productive, sustainable, and inclusive world. We challenge ourselves to create an inclusive way of working where we are open to new ideas, empowered to take risks and fearless to bring our authentic selves to work What we offer Nokia offers continuous learning opportunities, well-being programs to support you mentally and physically, opportunities to join and get supported by employee resource groups, mentoring programs and highly diverse teams with an inclusive culture where people thrive and are empowered. Nokia is committed to inclusion and is an equal opportunity employer Nokia has received the following recognitions for its commitment to inclusion & equality: One of the World’s Most Ethical Companies by Ethisphere Gender-Equality Index by Bloomberg Workplace Pride Global Benchmark At Nokia, we act inclusively and respect the uniqueness of people. Nokia’s employment decisions are made regardless of race, color, national or ethnic origin, religion, gender, sexual orientation, gender identity or expression, age, marital status, disability, protected veteran status or other characteristics protected by law. We are committed to a culture of inclusion built upon our core value of respect. Join us and be part of a company where you will feel included and empowered to succeed. About The Team Nokia Bell Labs is the world-renowned research arm of Nokia, having invented many of the foundational technologies that underpin information and communications networks and all digital devices and systems. This research has produced nine Nobel Prizes, five Turing Awards and numerous other awards.

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. IPPD: Physical design engineer Physical Implementation activities for high performance Cores for 16/14/7/5nm or lower technologies, which includes all or some of the below. Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), Low Power verification, PDN, Timing Closure and / or power optimization Exposure to PD implementation of PPA critical cores. Exposure to timing convergence of high frequency data-path intensive Cores and advanced STA concepts. Able to handle Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes. Understanding of clocking architecture. Tcl/Python/Perl Scripting aware for small automation Strong problem-solving skills , good communication skills and good team player Collaborate with design, DFT and PNR teams and support issue resolutions wrt constraints validation, verification, STA, Physical design, etc. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3069942

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Job responsibilities: Able to lead IP/Sub-System/Soc Team as Overall Project Functional Lead (PFL) Study industry standard methodologies and quickly implement same in the team Develop test plans, tests and verification infrastructure for complex IP/sub-system/SOC Expertise in end to end Logic Verification Process including Verification Planning, Functional Coverage planning and development, Test case development, regression, debug and Coverage closure Create verification environment using UVM methodology Create reusable bus functional models, monitors, checkers and scoreboards Drive functional coverage driven verification closure. Work with architects, designers, and post-silicon teams Expertise in SVA development like coding, porting and maintaining System Verilog Assertions and Formal Verification Guide junior members , lead projects and manage global stakeholders Define state of the art Logic Verification methodology and participate in innovation and initiatives Development of tools for Design and Verification support. Debug failures and root-cause it by interacting with other teams/groups Etc. Qualifications 13+ Years of the relevant work experience Education: B.E/B.Tech/M.Tech in ECE/VLSI/Electrical Engineering Skills Required/Preferred (SRAM/DRAM/ROM/ Flash ) Circuits/Logic Software Skills Required: Proficiency in Computer Science fundamentals – object oriented design, data structures, algorithms, design, problem solving, and complexity analysis Basic knowledge of with c, c++, SystemC, perl, python, tcl, shell is preferable Functional Verification: Unit/Sub-system/SOC level verification experience Experience in leading verification closure of complex IP/SOC for at least one project Exposure to industry standard verification tools for simulation and debug RTL & Gate Level Simulations, RNM Verification Proficiency in Verilog, System Verilog , Assertions and UVM Exposure to Verification Fundamentals Verification Automation using scripts like Python, Perl,shell,tcl/tk Good debugging and problem solving skills. Good communication skills and ability, desire to work as a team player Exposure to Analog verification will additional plus point -Digital design Concepts CMOS VLSI, Digital Circuits Knowledge on Memory (preferred) Preferred exposure NCSIM, Xcellium, IMC, IEV, Verdi, Jasper, VS Formal, vManager Cadence Schematic and layout environment Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at jobs.accommodations@sandisk.com to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SENIOR SILICON DESIGN ENGINEER The Role Join AMD as we push the boundaries of what's possible in graphics and compute technology. We are seeking a talented RTL Physical Design Engineer to contribute to the development and optimization of our cutting-edge CDNA and RDNA graphics IP. This role involves transforming sophisticated RTL designs into robust and efficient physical layouts, critical to the performance of our next-generation graphics and compute solutions. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Key Responsibilities Physical Design Implementation: Translate complex CDNA and RDNA graphics IP RTL designs into optimized physical layouts. Utilize industry-leading EDA tools for synthesis, place-and-route (PnR), and physical verification processes to take the design thru mock-taepout Performance Optimization: Focus on power, performance, and area (PPA) optimization to meet the stringent requirements of high-performance graphics and compute products. Collaborate with architecture and front-end design teams to align RTL design with physical constraints and objectives. Verification and Timing Closure: Conduct static timing analysis (STA) to ensure robust timing closure and sign-off for graphics IP. Implement and verify design rule checks (DRC), layout versus schematic checks (LVS), and power grid analysis tailored to CDNA and RDNA requirements. Collaboration and Communication: Work closely with cross-functional teams, including architects, RTL designers, and verification engineers to ensure seamless integration and functionality of graphics IP cores. Provide feedback and suggest improvements to design methodologies and processes to push the technology envelope further. Documentation and Reporting: Maintain comprehensive design documentation, methodologies, and updates. Prepare detailed reports on design progress, performance metrics, and any technical challenges encountered. PREFERRED EXPERIENCE: Domain Expertise: Experience with working on complex design and optimizing for performance, power, and area. Technical Proficiency: Proven track record in RTL synthesis, place-and-route (PnR), and static timing analysis (STA) for complex IP cores. Proficiency with industry-leading EDA tools, such as Synopsys Design Compiler, Cadence Innovus, and timing analysis tools like PrimeTime. Experience with low-power design methodologies and techniques for high-performance graphics IP. Design and Verification: Successful completion of full-chip sign-off, including design rule checks (DRC) and layout versus schematic (LVS) checks. Strong skills in signal integrity analysis, including crosstalk and IR drop evaluations. Process Technology: Experience working with advanced semiconductor process nodes (e.g., 7nm, 5nm, or below). Knowledge of process-related challenges and optimization techniques for graphics applications. Scripting and Automation: Proficiency in scripting languages such as Perl, Python, or TCL to automate design flows and improve efficiency. Experience developing and maintaining scripts for design rule checks and optimization processes. Problem-Solving and Innovation: Demonstrated ability to solve complex design challenges using innovative approaches. A track record of contributing to the improvement of design techniques and methodologies in a graphics-focused engineering team. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Senior Silicon PD CAD Engineer Bangalore, Karnataka, India + 1 more location Date posted Jul 16, 2025 Job number 1844305 Work site Up to 50% work from home Travel 0-25 % Role type Individual Contributor Profession Hardware Engineering Discipline Silicon Engineering Employment type Full-Time Overview Microsoft’s Azure Hardware Systems and Infrastructure team are at the forefront of the technology revolution, driving the development and deployment of cutting-edge cloud infrastructure solutions. Within our Silicon Engineering team, you will have the opportunity to work with some of the brightest minds in the industry to help shape the future of Artificial Intelligence and Computing. Being the PD CAD Engineer, you will be at the forefront of solving complex problems and building systems that require a deep understanding of hardware and software principles; and collaborate with cross-functional teams to deliver solutions that meet the needs of our world class Silicon Engineering teams worldwide. You will be building smart and efficient CAD solutions for the infrastructure, design-flows, Quality checks & Analytics and pioneering, path-clearing & deploying the latest EDA technologies related to Physical design Implementation, various sign-offs requirements and SOC tape-out flows. We are committed to a diverse and inclusive workspace and strongly encourage applicants from all backgrounds and walks of life. Differences make us better! Come and be part of the making of the World’s Computer! #SCHIE #AHSI Qualifications Required Qualifications: 7+ years of EDA tools’ expertise in Cadence, Synopsys and/or other equivalent tools 4+ years of programming skills in (any of) the following languages: Python, TCL, Perl, SQL, UNIX bash/Makefile Knowledge of Physical Design CAD flows/tools Knowledge and good understanding of RTL2GDSII physical design and sign-off flows Exposure to Silicon design setup/environment, various design flows and methodologies used for silicon product development Preferred Qualifications: Having as many of these specific qualifications is a plus, but transferable skills/experiences may be equally valuable. Master’s degree in computer or electrical engineering with a specialization in VLSI Solid scripting experience in Python, TCL & shell Hands-on experience in two or more functional domains such as Synthesis, Power grid development, Design Planning, Place and Route, Static Timing Analysis, Physical verification, EMIR. Physical design experience on advanced nodes Hands-on experience with flow orchestration tools such as Altair FlowTracer, and compute batch schedulers such as Altair Accelerator. Experience in building & maintaining PD CAD flows Solid experience in driving & working closely with EDA partners to improve their offerings Responsibilities In this role you will: Develop and support the CAD flow for Top Level, Synthesis, Place and Route (PnR) and Signoff. Work with design teams to understand requirements and enable scalable solutions. Engage with EDA in providing cutting edge single-box solutions for multi-scenario Maximize design productivity with strong/efficient scripting skills and customization of tool flows Perform in-depth root-cause analysis, issue debug and qualification for Microsoft’s broad Silicon portfolio. Collaborate with EDA partners to determine/drive optimal and cutting-edge solutions for effective & efficient CAD solutions Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.  Industry leading healthcare  Educational resources  Discounts on products and services  Savings and investments  Maternity and paternity leave  Generous time away  Giving programs  Opportunities to network and connect Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Noida, Uttar Pradesh, India Category: Engineering Hire Type: Employee Job ID 10849 Date posted 07/16/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are passionate about solving complex problems at the intersection of software engineering and semiconductor technology. Your curiosity drives you to explore new solutions and approaches, especially in high-impact areas such as memory characterization and automation. With a strong foundation in computer science, electronics, or a related discipline, you thrive in environments where collaboration, innovation, and technical excellence are valued. You are detail-oriented, analytical, and always eager to learn and adapt as technology evolves. You take pride in building robust, maintainable code and are committed to delivering quality solutions that make a tangible difference. As a team player, you communicate clearly, seek feedback, and contribute to a culture of openness and continuous improvement. Whether working independently or in cross-functional teams, you bring a sense of accountability and ownership to your work. You are excited by the prospect of impacting the next generation of semiconductor products and motivated by the opportunity to drive productivity and efficiency through automation. If you are ready to challenge yourself, innovate, and help shape the future of memory IP development, Synopsys is the place for you. What You’ll Be Doing: Designing and developing robust software tools for automating memory characterization workflows, including simulation setup, data extraction, and report generation. Collaborating closely with memory design, CAD, and validation teams to understand requirements and implement solutions that enhance accuracy, scalability, and performance of characterization flows. Integrating EDA tools such as SPICE simulators, Liberty format analyzers, and waveform viewers into advanced automation flows. Optimizing simulation execution on large compute clusters and efficiently managing the vast data sets generated during memory characterization. Building modular, maintainable, and high-performance codebases using C++, Python, Shell/TCL scripts, and industry-standard software engineering tools. Contributing to the development of test infrastructure, debugging tools, and validation methodologies to ensure the correctness and consistency of characterization results. Participating in code reviews, providing innovative ideas, and driving improvements in productivity and tool efficiency across the team. The Impact You Will Have: Accelerate the delivery of high-performance memory compilers for advanced technology nodes (e.g.,5nm,3nm, and beyond), enabling cutting-edge products. Streamline and automate engineering flows, reducing manual effort and enhancing productivity for multidisciplinary teams. Enhance the quality and reliability of characterization data, directly contributing to Process Design Kits (PDKs), EDA tools, and customer deliverables. Drive innovations that improve cost-efficiency, scalability, and competitiveness of Synopsys’ global IP portfolio. Contribute to the continuous improvement of internal infrastructure, processes, and best practices, fostering a culture of technical excellence. Empower internal and external customers through robust, user-friendly tools that enable faster, more reliable delivery of semiconductor solutions. What You’ll Need: B.Tech/MTech in Computer Science, Electronics, or a related field. At least 2 years of experience in software development or EDA tool development, preferably within the semiconductor industry. Proficiency in C/C++, TCL, Python, SQL, and scripting languages such as Shell. Experience with debugging tools such as GDB, and memory debugging tools like Valgrind or Purify. Strong understanding of machine learning algorithms (supervised, unsupervised, reinforcement learning). Hands-on experience with Python ML libraries such as scikit-learn, TensorFlow, or PyTorch. Who You Are: Detail-oriented with excellent analytical and problem-solving abilities. Possess strong verbal and written communication skills, able to articulate complex technical concepts clearly. A collaborative team player who thrives in cross-functional and multicultural environments. Demonstrates accountability and ownership in delivering high-quality work. An innovative thinker passionate about technology, automation, and continuous learning. The Team You’ll Be A Part Of: You’ll be joining a dynamic and forward-thinking team dedicated to developing and maintaining advanced memory characterization tools for next-generation semiconductor technologies. The team is known for its strong collaboration across domains such as software, CAD, and design, and for fostering a culture of inclusivity and openness. Committed to continuous improvement, the team values innovation and feedback while delivering high-quality, impactful solutions that empower both internal teams and external customers. Together, you will be driving the future of memory IP development by solving complex challenges and pushing the boundaries of performance, scalability, and automation. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.