Staff ASIC Verification Engineer, Noida Location: Key responsibilities: Participate in development of verification test plan, verification environment documentation and test environment usage documentation Evaluates and exercises various aspects of the development flow. May include such items as Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modelling, and verification coverage metrics (functional coverage and code coverage) Collaborate with architect, designers , VIP team and peers to accomplish all verification goals. Identify design problems, possible corrective actions and/or inconsistencies on documented functionality Adhere to quality standards and good test and verification practices. May work to coach junior engineers and help them in debugging complex problems. Key Qualifications Proven desire to learn and explore new state of the art technologies Demonstrate good written and spoken English communication skills Demonstrate good review and problem-solving skills Knowledgeable with Verilog, VHDL and/or SystemVerilog Knowledgeable with scripting languages (BASH/TCSH/PERL/PYTHON/TCL) is a plus Understanding of verification methodology such as UVM . Good organization and communication skills. 5 + years of relevant experience Show more Show less

Alternate Job Titles: Digital Verification Specialist Functional Verification Engineer Verification Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and meticulous Digital Verification Engineer with a keen interest in functional verification of High Speed interface IPs. With a dynamic personality and a strong eagerness to learn, you are driven to excel in Pre-silicon verification activities. Your understanding of digital design and HDL implementation sets you apart, and you thrive in environments where you can build and update verification plans and test cases. You are well-versed in scripting and automation using TCL, PERL, or Python, and possess excellent debug and diagnostic skills. Collaboration with digital designers is second nature to you, ensuring you achieve the desired coverage and performance in your projects. Your innovative mindset and commitment to excellence make you an invaluable asset to any verification team. What You’ll Be Doing: Work on Functional Verification of High speed serial link PHY IPs for USBx, PCIex, Ethernet, Display & HDMI protocol standards Study IP/design blocks/Firmware Specifications and build/update verification plans as well as the test cases Build/update functional verification environments to execute the test plans Implement checkers, assertions, random test generators, high level transactional models, and bus functional models (BFMs) as per the verification plan needs Perform simulation, random and direct stimulus development, and coverage review Work closely with digital designers for debug and achieve the desired coverage The Impact You Will Have: Ensure the reliability and performance of High Speed interface IPs, critical to various advanced technologies Contribute to the development of cutting-edge verification methodologies Enhance the quality and efficiency of verification processes Collaborate effectively with cross-functional teams to achieve project goals Drive innovation in verification techniques, improving overall product quality Support the creation of high-performance silicon chips that empower modern technology What You’ll Need: B.Tech/M.Tech with 3+ years of relevant experience Understanding of functional verification flow with awareness of verification tools and methodologies such as VMM, OVM/UVM, and System Verilog Proficiency in scripting and automation using TCL, PERL, or Python Strong debug and diagnostic skills Experience in building and updating verification environments and test plans Who You Are: Detail-oriented with a strong analytical mindset Excellent communicator and team player Proactive problem-solver with a passion for innovation Adaptable and eager to learn new technologies Highly organized and capable of managing multiple tasks The Team You’ll Be A Part Of: You will be part of a dedicated team focused on the functional verification of high-speed interface IPs. Our team is committed to excellence and continuous improvement, working collaboratively to achieve the highest standards in verification processes. We value innovation, teamwork, and a results-driven approach, ensuring that our contributions significantly impact the success of our projects and the advancement of technology. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

We are hiring for- Role: PLM Enovia Consultant Experience: 5+ Years Location: Hyderabad Required skills: Enovia. TCL Matrix. JPO, UI3 components, 3DExperieance Dassault Systemes Key Responsibilities: Requirements Gathering: Ability to communicate with the users to identify the requirements and perform feasibility study on the business needs. PLM Development and Enhancements: Deliver development efforts based on story points in user stories and features Continuous Improvement: Identify and implement optimizations to improve system performance, stability and user experience -- Muugddha Vanjarii 7822804824 mugdha.vanjari@sunbrilotechnologies.com

Hi All, Greetings' from Eximietas Design....! We are Hiring ASIC SOC RTL Design Engineer/Leads. Job Title: ASIC SOC RTL Design Engineer/Leads ..! Experience: 10+ Years. Location: Vizag or Bangalore. Job Description: Eximietas Design is seeking an experienced and highly skilled ASIC SOC RTL Design to join our growing team. As a key contributor, you will play a critical role in defining and implementing the microarchitecture of cutting-edge semiconductor designs. You will work on complex RTL design challenges, collaborate with cross-functional teams, and contribute to the delivery of high-performance, power-efficient, and innovative solutions. Key Responsibilities: Define and develop microarchitecture specifications for complex SoC designs. Lead RTL design and implementation using Verilog/SystemVerilog, ensuring optimal performance, power, and area (PPA). Collaborate with system architects, verification teams, and physical design teams to ensure successful project execution. Perform design trade-off analysis to meet functional, performance, and power requirements. Develop and implement design methodologies to improve efficiency and quality. Mentor and guide junior engineers, fostering a culture of innovation and excellence. Participate in design reviews, provide technical leadership, and ensure adherence to project timelines. Qualifications: 10+ years of hands-on experience in RTL design and microarchitecture development. Strong expertise in RTL design using Verilog/SystemVerilog and logic synthesis . Proficiency in microarchitecture design for complex SoCs, including pipelining, caching, and memory subsystems . Experience with low-power design techniques (e.g., clock gating, power gating, multi-Vt optimization). Familiarity with advanced process nodes and their specific challenges (e.g., finFET, multi-patterning). Strong scripting skills in Tcl, Python, or Perl for automation and flow development. Excellent problem-solving skills and attention to detail. Strong communication and leadership skills. What We Offer: Opportunity to work on cutting-edge semiconductor designs and innovative technologies. Collaborative and inclusive work environment. Competitive compensation and benefits package. Professional growth and development opportunities. Interested Engineers please share your updated resume : maruthiprasad.e@eximietas.design Show more Show less

The position involves designing, developing and deploying UVM based Testbenches for multi-core, multi-threaded processor subsystems with emphasis on verifying and signing off performance and power along with functionality. The candidate should have worked on architecture of chip-level testbenches and verification of SoCs and chipsets with ARM Cortex and proprietary processor technology and AMBA AHB/AXI/APB along with peripheral interfaces like SDIO, UART, I2S, I2C, PWM, QEI, Experience Level: 5-15 years Education Requirements: B.Tech/M.Tech in ECE, EEE Minimum Qualifications: Develop and signoff on test plans and test cases Strong knowledge of digital design and AMBA AHB/AXI/APB based SoC Architecture strong knowledge of Verilog, System Verilog, UVM, C/C++ Experience in usage of assertions, constrained random generation, functional/code coverage Knowledge of scripting languages like Perl, Python, Tcl, shell to achieve automation of verification methodologies and flows Analytical debugging skills Knowledge on C Based Testcases Knowledge of SoC,Memory and Cache Architectures Preferred Qualifications: Knowledge of high-speed interfaces like Quad/Octa-SPI Knowledge of peripheral interfaces like SDIO, UART, I2S, I2C, PWM, QEI, CAN Knowledge of wireless technologies like WLAN, Bluetooth, ZigBee Mentoring skills Exceptional problem-solving skills Good written and oral communication skills Show more Show less

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: DV Engineers PCIe (either IP or SoC level experience) Location: Bangalore Work Type: Onsite Job Type: Full time Job Description: Experienced and motivated Senior Design Verification Engineer with a deep understanding of the PCIe protocol and hands-on experience in SystemVerilog and UVM. The ideal candidate will lead verification activities for complex PCIe subsystems or SoCs, and contribute to building scalable, reusable verification infrastructure. Key Responsibilities: Develop UVM-based verification environments for PCIe IPs or SoCs. Define and execute comprehensive verification plans for PCIe Gen3/Gen4/Gen5/Gen6 features. Drive testbench development, stimulus generation, scoreboarding, and coverage closure. Validate protocol compliance including LTSSM, TLP/DLLP, BAR/Address decoding, and interrupt mechanisms. Work closely with RTL, DFT, and system validation teams for debug and feature bring-up. Conduct assertion-based verification and participate in formal verification as needed. Collaborate with cross-functional teams to ensure successful first-silicon quality. Required Skills & Experience: B.E./B.Tech or M.E./M.Tech in ECE 8+ years of experience in ASIC/SoC design verification. Proven expertise in SystemVerilog, UVM, and complex testbench development. Deep knowledge of PCIe protocol (Gen3/Gen4/Gen5/Gen6). Experience in verifying Root Complex (RC) and Endpoint (EP) configurations. Familiarity with AMBA protocols (AXI, AHB) and memory-mapped IO. Proficiency with EDA tools like VCS, Questa, Verdi, SimVision. Strong debugging and analytical skills, particularly with PCIe protocol analyzers and simulation waveforms. Scripting proficiency in Python, Perl, TCL, or Shell for automation. Nice to Have: Knowledge of low power (UPF) and DFT concepts. Familiarity with Formal Verification, Portable Stimulus, or Emulation. Exposure to hardware validation, bring-up, or post-silicon debug. Domain experience in datacenter, storage, networking, or automotive industries. Soft Skills: Strong communication and documentation skills Problem-solving mindset and attention to detail Leadership in driving verification tasks and mentoring junior engineers TekWissen Group is an equal opportunity employer supporting workforce diversity.

About Marvell . Your Team, Your Impact Custom Compute and Storage (CCS) Business Unit closely collaborates with strategic customers in the development of advanced and highly complex SoCs, from architecture and design all the way through layout, packaging, prototype validation and production ramp up. The Emulation Center of Excellence (CoE) team is key part of this group, with global ownership and responsibility for delivering emulation infrastructure, validating the design on emulation and drive left shift of SW and post-silicon readiness for all of CCS products. As part of the Emulation CoE leadership, you will drive the emulation strategy, vendor platform enablement, testplan execution for a high quality design tape-out What You Can Expect Build and Lead a strong technical team of emulation experts to define emulation strategy and platform requirements, develop emulation testplan, and drive execution of the emulation verification for large CCS products on emulation platform such as Veloce, Zebu and Palladium. Work with various stakeholders to define the emulation HW requirements for CCS products, including platforms, hardware/software collaterals, transactors, speed-bridges etc. Work closely with emulation hardware vendor application engineers (AEs) to keep the emulation hardware, software ecosystem updated, drive debug and resolution of issues with the vendor and design team. Define and develop new capabilities HW/SW tools to enable acceleration of RTL and improve emulation/FPGA model usability for pre-Silicon and post-Silicon functional validation as well as SW development/validation Interface with and provide guidance to pre-silicon Validation teams for optimizing pre-Si validation environments, test suites and methodologies for emulation efficiency Develop and apply automation aids, flows and scripts in support of emulation ease of use and improvement of equipment utilization. What Were Looking For Bachelor s degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience or Master s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 10+ years of experience. Proven track record of managing technical teams and leading cross-functional teams for design emulation and verification. Substantial knowledge of emulation platforms offerings from various vendors such as Synopsys, Cadence, Siemens including extensive experience in building complex SOC emulation models Working knowledge in one or more of the following: Processor architecture, SOC components, SOC inter-connect buses, IO protocols (PCIe, CXL, Ethernet) and memory technologies interfaces (DDR, HBM) Strong understanding of product development process of large SOCs and verification/debug experience in emulation platforms. Strong experience in coding in scripting languages like Perl, Python, Tcl & UNIX Shell etc Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-CP1

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. GCS AE Job Description Document Job Title: Lead Application Engineer - GCS Location: Bangalore / Noida Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique “One Cadence – One Team” culture builds and fosters diversity, equity and inclusion to maximize our ability to innovate, drive growth, and win with our customers. Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day. Job Summary As a member of the GCS Organization for the MSA (Multiphysics System Analysis), you will partner with world-wide Cadence customers to provide post sales technical consultation for IC level Power System analysis products for implementing cutting-edge designs. This involves working closely with the customers to understand and debug complex issues enabling them to proceed further with design cycle phases, help them leverage the latest tool capabilities, and guide them with implementation of software in their design methodologies. You will have an opportunity to acquire both breadth and depth of technical knowledge, get wide exposure to the latest design practices in industry and demonstrate expertise by authoring high impact knowledge content. This role also provides opportunity to participate in the evolution of key technology solutions to the most pressing design problems. In this role, you will have the opportunity to work with product teams to identify and prioritize the product improvement initiatives with your timely feedback and observations. This an excellent opportunity to work in a supportive, flexible and friendly work environment that GCS offers, where we are vested in each other’s success, and are passionate about technology and innovation. Job Responsibilities Provide technical support for Voltus product from the Multiphysics System Analysis (MSA) toolset of Cadence products with focus on productivity, and customer satisfaction Support multiple tools/methods for customer requiring general domain knowledge and developing business experience Assist in creation of high quality and impactful knowledge content in MSA domain Work independently at Cadence or customer facilities to deliver quality results according to schedule requirements Work on problems of moderate scope that may require analysis of situations, data or tool problems Qualifications Bachelor’s Degree in; Electrical / Electronics / Electronics and Communication / VLSI Engineering with 5-7 years related experience OR Masters with 3-4 years of related experience OR PhD with 1 years of related experience Experience And Technical Skills Required 3-7 years relevant industry experience in EMIR analysis, PDN analysis with digital signoff tools and Digital Physical implementation as designer or methodology/flow expert Strong background in Digital logic Design, CMOS logic Design, Power IR drop analysis, Circuit Design and Analysis, Digital and Behavioral simulation fundamentals related to IC and Package Design Debugging of Low power and multiple power domain analysis for chip power integrity sign-off. Understanding of Digital design toolsets of Cadence (Genus/Innovus/Tempus/Conformal); knowledgeable of at least 50% of a given flow; detailed knowledge in one CDN tool, learning others; ability to analyze customer's environment and evaluate appropriate support solutions; learning competitive tools/technologies Must have excellent debugging skills and ability to separate out the critical issues from trivial ones. Ability to solve interface level problems emanating from IC Implementation side and System analysis side. Ability to debug Timing and thermal issues in relation to IR and EM is a plus Good understanding of Hardware description languages like VHDL, Verilog, System Verilog. Knowledge on TCL, Perl or Python scripting. Behavioral Skills Required Must possess strong written, verbal and presentation skills Ability to establish a close working relationship with both customer peers and management Explore what’s possible to get the job done, including creative use of unconventional solutions Work effectively across functions and geographies Push to raise the bar while always operating with integrity We’re doing work that matters. Help us solve what others can’t. Show more Show less

Optum is a global organization that delivers care, aided by technology to help millions of people live healthier lives. The work you do with our team will directly improve health outcomes by connecting people with the care, pharmacy benefits, data and resources they need to feel their best. Here, you will find a culture guided by inclusion, talented peers, comprehensive benefits and career development opportunities. Come make an impact on the communities we serve as you help us advance health optimization on a global scale. Join us to start Caring. Connecting. Growing together. The Role in BriefThe Data Integration Analyst, is responsible for implementing, maintaining, and supporting HL7 interfaces between customers, both external and internal, and Optum’s integration platforms. The Engineer will work in a team, but will have individual assignments that he/she will work on independently. Engineers are expected to work under aggressive schedules, be self-sufficient, work within established standards, and be able to work on multiple assignments simultaneously. Candidates must be willing to work in a 24/7 environment and will be on-call as needed for critical issues. Primary Responsibilities Interface Design and Development: Interface AnalysisHL7 message investigation to determine gaps or remediate issues Interface Design, Development, and Delivery - Interface planning, filtering, transformation, and routing Interface ValidationReview, verification, and monitoring to ensure delivered interface passes acceptance testing Interface Go-Live and Transition to SupportCompleting cutover events with teams / partners and executing turnover procedures for hand-off Provider EnrollmentsProvisioning and documentation of all integrations Troubleshooting and Support: Issue ResolutionTroubleshoot issues raised by alarms, support, or project managers from root cause identification to resolution Support RequestsHandle tier 2 / 3 support requests and provide timely solutions to ensure client satisfaction Enhancements / MaintenanceEnsuring stable and continuous data delivery Collaboration and Communication: Stakeholder InteractionWork closely with Clients, Project Managers, Product managers and other stakeholders to understand requirements and deliver solutions DocumentationContribute to technical documentation of specifications and processes CommunicationEffectively communicate complex concepts, both verbally and in writing, to team members and clients Comply with the terms and conditions of the employment contract, company policies and procedures, and any and all directives (such as, but not limited to, transfer and/or re-assignment to different work locations, change in teams and/or work shifts, policies in regards to flexibility of work benefits and/or work environment, alternative work arrangements, and other decisions that may arise due to the changing business environment). The Company may adopt, vary or rescind these policies and directives in its absolute discretion and without any limitation (implied or otherwise) on its ability to do so Basic Qualifications EducationBachelor’s degree in Computer Science or any engineering field Experience2+ years of experience working with HL7 data and Integration Engines or Platforms Technical AptitudeAbility to learn new technologies Skills: Proven solid analytical and problem-solving skills Required Qualifications Undergraduate degree or equivalent experience HL7 Standards knowledgeHL7 v2, v3, CDA Integration Tools knowledgeInter Systems IRIS, Infor Cloverleaf, NextGen Mirth Connect, or equivalent Cloud Technology knowledgeAzure or AWS Scripting and StructureProficiency in T-SQL and procedural scripting, XML, JSON Preferred Qualifications HL7 Standards knowledge HL7 FHIR, US Core Integration Tools knowledge Inter Systems Ensemble or IRIS, Cache Scripting and Structure knowledge Object Script, Perl, TCL, Java script US Health care Knowledge Health Information SystemsWorking knowledge Clinical Data Analysis knowledge Clinical ProcessesUnderstanding of clinical processes and vocabulary Soft Skills Analytical and CreativeHighly analytical, curious, and creative OrganizedProven solid organization skills and attention to detail OwnershipTakes ownership of responsibilities At UnitedHealth Group, our mission is to help people live healthier lives and make the health system work better for everyone. We believe everyone-of every race, gender, sexuality, age, location and income-deserves the opportunity to live their healthiest life. Today, however, there are still far too many barriers to good health which are disproportionately experienced by people of color, historically marginalized groups and those with lower incomes. We are committed to mitigating our impact on the environment and enabling and delivering equitable care that addresses health disparities and improves health outcomes — an enterprise priority reflected in our mission.

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-6years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

1. Hands on work on custom layout for analog blocks like High Speed SerDes and General purpose IO designs with Cadence Virtuoso on latest technologies like 5nm and below and also take leadership roles in delivery of IPs 2. Work on Floor planning, power design, signal routing strategy, EMIR awareness andparasitic optimisations 3. Understand and apply analog Layout techniques to ensure the design meets performance with minimum possible area and good yield. 4. Participate in building and enhancing layout flow for faster, higher quality design process. 5. Checking physical verifications like DRC/LVS/ERC/ANT/DFM and other IBM internal checks 6. Collaborate with Circuit Designers to solve challenging problems 7. Writing /PYTHON scripts to automate repetitive tasks 8. Work with Place and Route engineer to integrate custom macros into top level. 9. Able to perform design reviews across global team 10. Work closely with required global teams to ensure the success of the whole product. 11. Leadership in delivery of macros we plan to own from India Job requirements: 1. Experience in doing layouts for analog blocks like SerDes, ADCs, DACs, LDOs, PLLs, BGAP & amplifiers etc. 2. Experience in designing layouts for high-speed circuits is a plus. 3. Layout experience in the following technology nodes3nm, 5nm and 7nm FinFET. 4. Good team worker with multi-discipline, multi-cultural and multi-site environments 5. Strong fundamental knowledge in semiconductor device physics, layout principles, IC reliability and failure mechanisms 6. Good problem-solving skills are essential where problems are analysed upfront, identifying gaps, and providing optimum solutions7. Knowledge in Skill/perl/tcl/Python scripting is a plus. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise The Analog layout design engineer with experience in next generation Ultra high speed serial IO link (HSS) interface for Cognitive, ML,DL, and data center applications. The engineer needs to have knowledge in the design and development full custom analog layouts for ultra high speed 32G/50G/112G IO link interfaces. Preferred technical and professional experience Experience in 7 and 14 nm analog layout design. Working on Cutting edge technology and HSS domain . Quick learner, deep layout design knowledge, problem solving skills and good communication skills with cross teams across the Geos.

We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBM’s microprocessor chip design team. As a member of functional DFT team ( Power on Reset, Architecture Verification Program, Array BIST teams ), you will be required but not restricted to pattern generation, simulation, validation, characterization, delivery to TAE, IBM’s Hardware Bring-up and Silicon Debug Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5-9 years experience in DFT on complex designs involving scan insertion, compression, MBIST, ATPG, simulations and IP integration and validation.Proven expertise in analysing and resolving DRCs/TSVs .Hands-on experience in pattern generation for various fault models, pattern retargeting and debugging techniques to address low coverage issues.Hands-on experience with Gate-Level DFT verification, both with and without timing annotations.Well versed with industry standard test techniques and advanced DFT features like SSN, IJTAG, IEEE 1500, Boundary scan , LBIST and STA constraint delivery .Hands on experience on industry standard tools used for DFT featuresProficiency in scripting languages such as TCL, Perl or Python to automate design and testing tasks.Worked with cross functional teams like design, STA & tester teams for ensuring top quality of DFT deliverables and DFT support and hand offs.Excellent analytical and problem-solving skills, with a keen attention to detail.Strong communication and collaboration skills, with the ability to work effectively within cross-functional teams Fundamentals in micro controller architecture, embedded firmware, functional verification and RTL design * Experience working with ATE engineers for silicon bring up, silicon debug and validation. * Experience in processor flow and post silicon validation Preferred technical and professional experience Hiring manager and Recruiter should collaborate to create the relevant verbiage.

Hello Visionary! We know that the only way a business thrive is if our people are growing. That’s why we always put our people first. Our global, diverse team would be happy to support you and challenge you to grow in new ways. Who knows where our shared journey will take you? We are looking for Software Developer You’ll make a difference by: Collaborating with global software product teams, comprising architects and developers To function in an efficient SAFe scrum team, where the work-life balance is very effective too Being part of a highly disciplined and influential work culture, where an individual's decision and contribution directly attribute to the success factor of the project Developing and to release a versatile and a robust software infrastructure platform, for more sophisticated tools to be built on top. Taking an ambitious role in the Product Quality & Reliability Assurance of a cloud-based offering with an easy-to-use interface that monitors, analyzes, and helps to optimize energy utilization of the buildings & campuses – via multi-site performance dashboards visualizing historical and near real-time series data for energy consumption, costs, and emissions values Developing and implementing the comprehensive test plans and strategies to validate software functionality and ensure compliance with established quality standards. Crafting and completing automated test scripts using JavaScript E2E testing frameworks such as Playwright or Cypress or TestCafe to facilitate early detection of defects and quality issues. Conducting visual regression and snapshot testing using Playwright. Performing API testing using tools like Postman and Playwright, ensuring robustness and reliability of backend services. Engaging in contract testing using PACT to validate interactions between services. Collaborating closely with developers to conduct root cause analysis for identified defects, providing detailed information to support defect resolution. Continuously improve testing processes and methodologies to enhance software quality and reliability. Use GitLab and pipelines for version control and CI/CD processes. You’ll win us over by: BE/B. Tech/ M.Sc. / MCA - (in Electrical, Mechanical, Electronics, Instrumentation, Mechatronics, Computer Science, or Information Technology or equivalent). Holding 3 years of demonstrated ability of IT software verification and validation. Having excellent hands-on experience and willingness in writing test cases, for web applications Proficiency in frontend automation using JavaScript E2E testing frameworks (TestCafe, Playwright or Cypress) Having experience with visual regression and snapshot testing Solid API testing skills with tools, like Postman and Playwright Familiarity with contract testing, like PACT Working experience in GitLab and CI/CD pipelines Having good knowledge in QA principles, methodologies, and standard processes Effectively communicate in English, both written and spoken Potential to learn and to be self-motivated Proactiveness, enough to share knowledge, to voice out problems and to ask for help Passion towards programming, technology and problem solving Desirable to have Proven Understanding of Test management tools such as IBM Jazz, JIRA… Hands-on experience in scripting languages, like Python, Perl, or TCL Hands-on experience in tools, like Robot or Selenium ISTQB certification (Foundation) Working experience in cross platform product verification Working experience in agile software development (daily scrum, pair sessions, sprint planning, retro & review and self-organized), configuration, testing and release management International experience and communication, including a collaboration in virtual international teams Expertly and pragmatically approaching demeanor to any situation Create a better #TomorrowWithUs! This role, based in Pune, is an individual contributor position. You may be required to visit other locations within India and internationally. In return, you'll have the opportunity to work with teams shaping the future. At Siemens, we are a collection of over 312,000 minds building the future, one day at a time, worldwide. We are dedicated to equality and welcome applications that reflect the diversity of the communities we serve. All employment decisions at Siemens are based on qualifications, merit, and business need. Bring your curiosity and imagination, and help us shape tomorrow Find out more about the Digital world of Siemens here: www.siemens.com/careers/digitalminds Find out more about Siemens careers at: www.siemens.com/careers Show more Show less

Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. As a Design Verification Engineer, you will be part of a dynamic team working with the best in the industry, focused on developing innovative ASIC solutions for Meta’s data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based testbench development to verification closure. Along with traditional simulation, you will use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success. ASIC Engineer, Design Verification Responsibilities: Develop functional tests based on verification test plan. Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage. Debug, root-cause and resolve functional failures in the design, partnering with the design/arch team. Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality. Minimum Qualifications: Currently has, or is in the process of obtaining a Bachelor's degree in Electronics Engineering, Computer Engineering, Computer Science, VLSI, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta. Experience using constrained-random, coverage driven verification or C/C++ verification. Experience in verifying a IP block using standard DV based techniques. Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments. Understanding in at least one of the following areas: computer architecture, CPU, GPU, networking, interconnects, fabrics or similar designs. Preferred Qualifications: Currently has, or is in the process of obtaining, a Master’s degree in Electronics Engineering, Computer Engineering, Computer Science or similar technical field. Experience in development of SystemVerilog/UVM based verification environments from scratch. Experience debugging fails to the line of RTL, closing out bug fixes, using Verdi or equivalent debug tools. Experience in verification of any peripheral IPs like UART, SPI, I2C and exposure to protocols like APB, AXI Experience working in a CPU/GPU environment. Experience with revision control systems like Mercurial(Hg), Git or SVN. About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics. Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta. Show more Show less

Our creative and versatile Physical Design team in Bangalore, India. As a member of this team you will be involved in creating next generation innovative networking chips in advanced process node. You will drive the backend process through the entire RTL 2 GDS Implementation flow including hierarchical floor planning, place & route, timing closure, power integrity, static timing verification, physical verification and equivalence checks, with special focus on performance & die size optimization. What you will do: Analyzes current generation quality and efficiency gaps to identify proper incremental or evolutionary changes to the existing physical design related Tools, Flow and Methodology. Work closely with various teams such as physical design, RTL, DFT, tool/flow owners, and EDA vendors to improve physical design methodologies. Good understanding of different CTS strategies and providing the feedback to Implementation Team. As member of physical design team, drive methodologies and “best known methods” to streamline and automate physical design work. STA setup, convergence methodology, reviews and sign-off for Multi-Mode and Multi-corner designs. Good at Timing ECO Implementation strategy development/convergence. Should have an experience in enabling the Tweaker/Primetime based ECO flows. Work on Automation scripts within STA tools for Methodology development Excellent debugging skills in implementation issues and ability to produce creative solutions. Evaluate multiple timing methodologies/tools on different designs and technology nodes. Good scripting skills (TCL/SHELL/PERL/Python) is a MUST Who you are: You are an ASIC engineer with 6+ years of related work experience with a broad mix of technologies including: All aspects of ASIC Physical implementation including Floor planning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration. Hierarchical design implementation approach, Timing closure, physical convergence. Power Integrity Analysis Experience with large designs (>100M gates) utilizing state of the art sub 16/14/7/5/3nm technologies. Familiarity with various process related design issues including Design for Yield and Manufacturability, multi-Vt strategies. You should also have hands on experience with the following Tool sets Floor planning and P&R tools: Cadence Innovus & Synopsys ICC2 Synthesis Tools: Synopsys DC/FC Formal Verification : Synopsys Formality and Cadence LEC Static Timing verification: Primetime-DMSA Power Integrity : Apache Redhawk Physical Design Verification Synopsys ICV, Mentor Calibre Scripting: TCL, Perl is required; Python is a plus Bachelor's degree in Telecommunications Engineering, Computer Science, MIS, or related experienceWe are looking for high achievers who love challenging environment to join our team. We Are Cisco #WeAreCisco, where each person is unique, but we bring our talents to work as a team and make a difference. Here’s how we do it. We embrace digital, and help our customers implement change in their digital businesses. Some may think we’re “old” (30 years strong!) and only about hardware, but we’re also a software company. And a security company. An AI/Machine Learning company. We even invented an intuitive network that adapts, predicts, learns and protects. No other company can do what we do – you can’t put us in a box! But “Digital Transformation” is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it.) Day to day, we focus on the give and take. We give our best, we give our egos a break, and we give of ourselves (because giving back is built into our DNA.) We take accountability, we take bold steps, and we take difference to heart. Because without diversity of thought and a commitment to equality for all, there is no moving forward. So, you have colorful hair? Don’t care. Tattoos? Show off your ink. Like polka dots? That’s cool. Show more Show less

Your future role Overall plant responsibility for production - process & quality. Ensure safety at work with ZERO Incidence rate. Achieve plants targets for productivity, OEE and KPI in all the control functions Operational control and control the cost as applicable Ensure the operational personal know and maintain behavior in accordance with company code of conduct Provide support to reporting personnel Ensure the correct application of Quality system instructions across operational areas in line with ISO-TS 16949 regulation, customer requirements ensuring the achievement of defined KPI Ensure the correct application adherence of environmental system ISO 14000 & Customer specific standard Drive environmental improvement programs in the plant. Ensure all maintenance activities of plant are conducted regularly. Team Management Your profile B.E. Mechanical/ Production (PG Preffered) 15 - 20 years of experience in similar work area (Aluminum Foundry/ Casting) with ISO/ TS background. Six Sigma & Lean manufacturing background expected. Good English communication skills Ability to work in Matrix Organization Strong analytical and quantitative competencies Understands complex concepts and the relationships between issues or problems Possesses intellectual agility; readily accepts the challenges of unfamiliar tasks

SKS Enterpprises is looking for Manager/ Sr Manager - Placement to join our dynamic team and embark on a rewarding career journey Career Counseling: Provide guidance and career counseling to students or job seekers, helping them identify their skills, interests, and career goals Job Placement: Facilitate job placements by matching candidates with suitable job openings based on their qualifications and preferences Employer Engagement: Build and maintain relationships with employers, businesses, and organizations to understand their hiring needs and requirements Job Postings and Recruitment: Post job vacancies and coordinate recruitment processes, including conducting interviews and coordinating selection procedures Resume and Interview Preparation: Assist candidates in preparing resumes, cover letters, and interview techniques to enhance their chances of securing a job Internship and Training Opportunities: Identify and promote internship and training opportunities for students and job seekers to gain practical experience Networking Events: Organize job fairs, networking events, and industry-specific workshops to connect candidates with potential employers

locationsIndia, Bangalore time typeFull time posted onPosted 9 Days Ago job requisition idJR0274850 Job Details: About The Role : We are looking for Senior DFT Design Engineers to join our team who are ready to make significant impacts in graphics and visual computing. As a member of the GHI DFT group, you will be responsible for one or more of the following activities: You will work on the design, RTL/GLS validation, automation, and/or timing analysis for Scan/ATPG and/or DFT/JTAG controller You will also contribute or be involved with trace/pattern generation efforts as well as post-silicon enabling, debug support, and/or analysis of the DFx features/content types you are responsible for. Develops the logic design, register transfer level (RTL) coding, and simulation for graphics IPs (including graphics, compute, display, and media) required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly across verification hierarchies, drives unit level verification, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high-quality integration of the GPU block. Qualifications: The ideal candidate will exhibit the following traits/skills: Excellent written and verbal communication skills Demonstrate Leadership ability in driving execution Demonstrate teamwork, problem solving and influencing skills Ability to work with different geographical locations Minimum Qualifications: Bachelors in Electrical/Computer Engineering or related field with 9+ years of experience. Or a Masters in the same fields with 7+ Years of academic or industry experience. Your experience should be in following At least one of the key DFT features such as TAP/JTAG, Scan/ATPG or Array DFT (MBIST/PBIST) (This is a key skill requirement.) SoC or IP DFT design, integration or verification EDA tools such as ATPG tools, Siemens Tessent shell, VCS simulation and/or debug tools. Preferred Qualifications: Silicon enabling debug or test pattern development experience Design automation skills and proficiency in programming or scripting languages Structural design flows, including timing, routing, placement or clocking analysis High volume manufacturing requirements and test flows 3D, media and display graphics pipelines SoC architecture Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

The Design Methodologies and Tools Engineer / Architect develops and applies Computer Aided Design (CAD) software engineering methods, theories and research techniques in the investigation and solution of technical problems. Assesses architecture and hardware limitations, plans technical projects in the design and development of CAD software. Defines and selects new approaches and implementation of CAD software engineering applications and design specifications and parameters. Develops routines and utility programs. Prepares design specifications, analysis and recommendations for presentation and approval. May specify materials, equipment and supplies required for completion of projects and may evaluate vendor capabilities to provide required products or services. Key Responsibilities Provide technical leadership to define, enable, implement, automate and drive tool/flow/methodology to improve SoC integration efficiency. quality, cost and predictability. Work with architects and design team to understand and continuously improve design process from specification to tapeout. Interface with the architecture, SoC integration, power, Design implementation, Power, Design Verification and Physical design teams to identify complex technical issues/risks and optimize the implementation efficiency and cost. Support the SoC Design and Integration team on project execution. You should be familiar with SoC level Clock and Reset, low power design, UPF, CDC/RDC/LINT, DFT, top level integration of connectivity, system bus, peripherals and processor. We are looking for someone who is technically hands on and a great team player. Preferred Experience Bachelor’s or Master’s degree in related discipline with 15+ years' experience preferred. Outstanding foundation in Systems & SoC architecture, with expertise in one or more of the following: SoC integration, Frontend-design, Design Verification, Design Emulation, System/performance/power modeling, Design handoffs, Design management, Design reuse, CAD/Automation algorithms. Experience analyzing Design and Verification methodologies/flows to identify bottlenecks, left-shift opportunities, and Demonstrated tools/flows/methodologies/automation expertise in SoC integration, Verification, Emulation, low power design, power optimization, Functional Safety, System modeling, Synthesis and anlysis. Experience with scripting in Perl, Python, TCL, and C/C++. Excellent communication and problem solving skills. Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies. The base salary range for this position is as mentioned below per year. We also provide competitive benefits, incentive compensation, and/or equity for certain roles. Company benefits include health. dental, and vision insurance. 401(k), and paid leave. Please note that the base salary range (OR hourly rate) is a guideline, and individual total compensation may vary based on a number of factors such as qualifications, skill level, work location, and other business and organizational needs. This base pay range is specific to California and is not applicable to other locations. A reasonable estimate of the base salary range as of the date of this posting is: $202,900 to $279,000 annually More information about NXP in the United States... NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals. Show more Show less

We are seeking a skilled SoC (System on Chip) Frontend Design Engineer to join our integrated circuit (IC) design team. The ideal candidate will be working on RTL design, digital logic design, synthesis, linting, timing analysis, and verification for FPGA/ASIC projects. This role requires deep knowledge of VHDL/Verilog, verification methodologies, testbench development, and debugging. The candidate will work closely with cross-functional teams to deliver high-quality, efficient SoC designs. You have: Bachelors Degree in Electrical, Computer Engineering, or a related field (Masters preferred).3+ years of experience in RTL design, digital logic design, and synthesis. Proficiency in VHDL/Verilog for RTL design. Strong knowledge of digital logic design, synthesis, and timing analysis. Experience with linting tools and methodologies. Familiarity with verification methodologies (UVM, System Verilog). Experience in testbench development, simulation, and functional coverage. Strong debugging skills to identify and resolve design issues. Proven track record of successful FPGA/ASIC design projects. Required ToolsSynopsys Design Compiler or Cadence Genus, Mentor Graphics QuestaSim, Spyglass VC It would be nice if you also had: Experience with advanced verification methodologies and tools. Familiarity with high-level synthesis (HLS) tools. Knowledge of scripting languages such as Python, Tcl, or Perl for automation. Develop RTL designs using VHDL/Verilog for FPGA/ASIC projects. Perform digital logic design, synthesis, and timing analysis. Conduct linting and static analysis to ensure code quality. Develop and implement verification methodologies (UVM, System Verilog). Create and maintain testbenches for simulation and functional coverage. Perform simulations and debugging to ensure design correctness. Participate in design reviews and provide feedback to improve design quality.

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Experience : 7 to 10 years Physical design of block level with full understanding of PnR cycle. Good understanding of Physical design fundamentals Good hands-on experience on industry standard pnr tools like ICC2/Innovus Good understanding on signoff tool like Prime time , Redhawk and calibre Should be able to guide junior engineers in resolving technical issues. Tools : ICC/Innovus, PT, StarRC, Redhawk, Calibre DRC/LVS Scripting: TCL, Perl Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3072524 Show more Show less

Job Purpose To Manage Information Security activities and ITSM processes related to Airport IT Operations. To ensure Security, Quality and Compliance of Systems, Services , Processes . To ensure IT Process Alignment with Business and Stakeholder Requirements To manage Information Security activities and Information Technology Services processes governance relating to IT Operations to ensure confidentiality, integrity and availability of systems, services and associated information are in tune with business and stakeholders needs and adhering to regulatory & statutory requirements ORGANISATION CHART Accountabilities Key Performance Indicators Strategy and Governance Reducing gap between current state and desired state to acceptable risks. Roll out corporate Initiatives as per corporate guidelines Propose, Review and Recommend cost-effective solutions Design and review Security Architecture Design and review Security Performance metricsReview Policy effectiveness No of Reviews No of Architectural Changes Information Risk Management Asset Classification Business Impact Assesments Threat and Vulnerability evalautions Risk Assesment and Risk Management Evaluate information security controls and countermeasures Integrate risk, threat and vulnerability identification and management into information management life cycle Vulnerabilities ManagementFormulate and Review Risk Acceptance Criteria No of Risks Identified/Mitigated No of Critical Incidents Information Security Program Development and management Identify and evaluate information security technologies, emerging trends Align information security architectures with changing business needs Develop information security standards, procedures and guidelines implement and communicate information security policies, standards, procedures and guidelines Design controls and review controls effectiveness Information security requirements are embedded into contracts and third-party management processes Design, implement and report security metrics for testing the effectiveness and applicability of information security controls No of deviations from Policy % compliance Key Accountabilities Accountabilities Key Performance Indicators Strategy and Governance, Reducing gap between current state and desired state to acceptable risks., Roll out corporate Initiatives as per corporate guidelines, Propose, Review and Recommend cost-effective solutions, Design and review Security Architecture Design and review Security Performance metrics Review Policy effectiveness No of Reviews, No of Architectural Changes Information Risk Management, Asset Classification, Business Impact Assessments, Threat and Vulnerability evaluations, Risk Assessment and Risk Management, Evaluate information security controls and countermeasures, Integrate risk, threat and vulnerability identification and management into information management life cycle, Vulnerabilities Management Formulate and Review Risk Acceptance Criteria, No of Risks Identified/Mitigated, No of Critical Incidents Information Security Program Development and management, Identify and evaluate information security technologies, emerging trends, Align information security architectures with changing business needs, Develop information security standards, procedures and guidelines implement and communicate information security policies, standards, procedures and guidelines ,Design controls and review controls effectiveness, Information security requirements are embedded into contracts and third-party management processes Design, implement and report security metrics for testing the effectiveness and applicability of information security controls. No of deviations from Policy,% compliance Information Security Incident Management, Manage Security operations center, Escalate unresolved issues, Schedule and Conduct Vulnerability, Penetration and Configuration tests and report findings and track findings to closure, Evaluate incident and problem related security incidents,, Security Log alerts review, Co-ordinate for forensics and analysis with vendor SLA, % Critical Incidents, Impact on CIA IT Service Delivery and Support, Implement Plan, do check and act management System, Design of ITIL compliant Process and Procedures, Rollout of ITIL compliant Process and Procedures, Design of Metrics and KPIs, Design of SLAs, Support IT services in floating RFPs and Proposals, Review Effectiveness of Metrics and KPIs, Awareness and Training, Customer Satisfaction Surveys, IT Services Complaints Management, Vendor and Supplier Performance Feedback, Configuration Audits, Change Manager / Service Delivery Manager (Governance),Asset Management ,Service Improvement Management No of Service Improvements, %Backlogs(Problem/Change),Adherence to BCP IS / IT Audit Process Management, ISO 20000/270001: ,Schedule Internal and External Audits, Internal auditor /management representative, Review audit findings, Conduct Management Review meetings, Corrective and preventive actions, Improve management systems, Compliance to respective Standards,, No of NCs,) KEY ACCOUNTABILITIES - Additional Details EXTERNAL INTERACTIONS External - Roles you need to interact with outside the organization to enable success in your day to day work Concessionaires/Regulatory Agencies /Airlines: Information Security Approvals for new service requests. Non-disclosure Agreements MDI Acceptance and awareness on Information Security Policy Regulatory and Legal Compliance Data privacy and Protections Incidents/Breaches Quality assurance Vendors Information Security Policy Compliance Physical and Environmental controls in use of facilities Review of Incidents/ Breaches Regulatory and Legal compliance Contracts and Procurement Info security guidelines Upgrades / Releases/Patches Security Bulletins Awareness and Training Vulnerability and Security Assessment tailored to business needs SLA Reviews Audits Event and log correlation Quality Assurance Implementation Partners: (Dubai Technology Partners, TCL, TTSL, BSNL, Pathfinder, IBM, KRONOS). Review for security policy compliance with Data and Privacy regulations Quality Assurance Implementation Partners: (Dubai Technology Partners, TCL, TTSL, BSNL, Pathfinder, IBM, KRONOS). Review for security policy compliance with Data and Privacy regulations Quality Assurance OEMs (UFIS, RESA, IER, SAFEGATE, BOSE, SIEMENS COMMUNICATION, SITA) : Performance Review SLA review Incidents and Problem review Legal and Regulatory compliance Security Policy compliance Quality Assurance INTERNAL INTERACTIONS Internal - Roles you need to interact with inside the organization to enable success in your day to day work Business units Aligning Business Requirements with security policy Awareness Programs Compliance and Regulatory Requirements Contractual requirements Human Resources Pre entry, entry and exit Physical and Environmental Requirements Business Continuity Tests Access Controls Quality Assurance Joint Venture Partners (HMACPL, HDFRL, NOVOTEL, FUEL FARM) : Security policy alignment with business requirements Security Awareness Regulatory and Legal compliance SLA Reviews Quality Assurance GHIAL employees Policy awareness Policies compliance Trainings Incident Reporting and Management Quality Assurance DIAL IT & Corporate IT: Share best practices CISO: Ensure corporate requirements are rolled out to business unit-GHIAL Review technological and business unit security requirements Quality Assurance FINANCIAL DIMENSIONS OPEX AOP SIEM Log monitoring and Compliance Cost optimization and Revenue maximizations assurance activities Other Dimensions Team size: 1 Customers : 130 End users : 1000+ (staff across HIAL, GADL & Other companies inside the campus using IT services) Education Qualifications Required B.E (Computers / Electronics /IT) Required Postgraduate in computer/ IT Required CRISC (Certified in Risk and Information Systems Control) / or CISA/ or CISM Desirable MBA Relevant Experience Minimum 9-11 Years in IT with at least 8 Years in Information security, quality and assurance functions COMPETENCIES Personal Effectiveness Social Awareness Entrepreneurship Problem Solving & Analytical Thinking Planning & Decision Making Capability Building Strategic Orientation Stakeholder Focus Networking Execution & Results Teamwork & Interpersonal influence Show more Show less

📍 Location: Hyderabad 💼 Experience: 10 to 20+ years 📢 Type: Full-Time | On-site About the Role: We are looking for a highly experienced and visionary Design Verification Leader to head our Full Chip Level Verification team. This is a strategic and hands-on role that will drive verification strategy, planning, execution, and team leadership across complex SoC/ASIC programs. You will work closely with architecture, design, DFT, and post-silicon validation teams to ensure first-pass silicon success, high quality, and on-time delivery. Key Responsibilities: Own and lead full-chip verification strategy, planning, and sign-off for multiple SoC/ASIC programs. Drive development and deployment of UVM-based testbenches , functional coverage, and formal verification strategies. Lead team(s) of engineers across domains, including IP, Sub-system, and SoC level verification. Collaborate with cross-functional stakeholders, including RTL design, DFT, firmware, validation, and architecture teams. Drive verification methodology standardization , automation, and reuse across programs. Deliver high-quality silicon by proactively identifying risks, debugging complex failures, and driving verification closure. Define and manage project schedules, resource allocation , and risk mitigation plans. Provide technical mentorship , performance reviews, and leadership to grow a world-class verification team. Represent the BU in technical reviews, customer discussions, and strategic planning. Required Skills and Experience: 10–20+ years of experience in ASIC/SoC design verification , with at least 5+ years in a leadership/managerial role. Strong hands-on experience with SystemVerilog, UVM, assertions (SVA), and functional coverage . Proven track record in full-chip and sub-system verification of complex SoCs or processors. Deep understanding of verification methodologies, flows, and tools (Synopsys, Cadence, Mentor). Strong debugging skills across simulation, emulation, and silicon bring-up. Experience with low-power verification (UPF), DFT-aware verification , and performance validation is a plus. Working knowledge of scripting (Python, Perl, Tcl) and regression infrastructure. Excellent project management, communication , and team leadership skills . BE/BTech or ME/MTech in Electronics, Electrical, or Computer Engineering. Preferred Qualifications: Experience working with global teams and customer engagements . Exposure to AI/ML, automotive, networking, or mobile SoC domains . Familiarity with formal verification and post-silicon validation techniques. Why Join Us? Lead cutting-edge semiconductor verification programs with global impact. Work with some of the brightest minds in VLSI and SoC development. Opportunity to drive strategy and build high-performance teams . Competitive compensation, leadership exposure, and career growth. Interested? 📧 Send your profile to hemant@sykatiya.com 📄 Let’s connect and explore how you can shape the future of silicon with us. Show more Show less

Summary Your role in our mission Essential Job Functions Performs testing, troubleshooting and analysis tasks on various phase(s) of network systems development including integration, systems testing, interoperability testing, field test plans and customer acceptance plans to maintain the credibility/viability of the system. Provides support for monitoring the initial configuration and parameters of equipment for system credibility. Assists in the investigation and resolution of matters of significance in conjunction with other engineering and technical support to ensure cost effective and efficient resolution of problems. Designs, develops, implements and maintains test processes and diagnostic programs for assigned projects. Works closely with team lead towards the completion of specifications and procedures for new products. Participates in writing test plans for assigned projects. Maintains record of test progress, documents test results, prepares reports and may present results as appropriate. Defines test cases and creates integration and system test scripts and configuration test questionnaires from functional requirement documents. Maintains defect reports and updates reports following regression testing efforts. Adheres to and advocates use of established quality methodology and escalates issues as appropriate. May work with clients to determine systems requirements. Assists lead engineer/management in writing proposals to recommend process/program and follows through on implementation. Basic Qualifications Bachelor's degree or equivalent combination of education and experience Bachelor's degree in computer science or engineering or related field preferred Three or more years of network testing experience Experience working with computer systems and their uses Experience working with telecommunications systems and their corresponding principles Experience working with network management and protocol system testing Experience working with scripting languages such as TCL, PERL, HP, etc Experience working with data transmission protocols such as TCP/IP, etc. Experience working with operating systems Experience working with protocols and technologies such as HTTP, SSL, FTP, SMTP, POP3, etc Experience working with network equipment: switches, routers, firewalls, intrusion detection systems, etc. Other Qualifications Good analytical and problem solving skills Good organization and time management skills Interpersonal skills to interact with customers and team members Communication skills Ability to work independently and as part of a team Willingness to travel Work Environment Office environment May require shift or weekend work What we're looking for What you should expect in this role Competency1 Competency2 Competency3 Competency4 Competency5 Show more Show less

As a DFT Engineer, you will be responsible for developing and implementing Design for Test methodologies for complex VLSI designs. You will ensure the testability and manufacturability of our products by working closely with design, verification, and physical design teams, Responsibilities: Develop and implement DFT architectures and strategies for complex SoC designs. Insert and verify DFT features such as scan chains, Built-In Self-Test (BIST) for memory and logic, and boundary scan (IEEE 1149.1/1149.6). Perform ATPG (Automatic Test Pattern Generation) and analyze coverage metrics to ensure high fault coverage. Collaborate with RTL designers to ensure seamless integration of DFT features into the design. Debug and resolve test-related issues in simulation, silicon validation, and production. Work closely with the physical design team to implement scan and clock constraints for timing closure. Optimize test time, power, and cost without compromising coverage and quality. Participate in silicon bring-up and post-silicon validation activities. Generate and maintain DFT documentation, including test plans, methodologies, and results. Requirements: Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. 4 to 10 years of experience in DFT for VLSI designs. Strong knowledge of DFT methodologies, including ATPG / MBIST / Scan Insertion Verilog/ System Verilog and scripting languages (Python, TCL, Perl). Solid understanding of STA concepts and constraints related to DFT. Experience in debugging silicon and ATE test patterns. Excellent problem-solving skills and ability to work in a collaborative environment. Familiarity with fault diagnosis and yield improvement methodologies. Exposure to advanced nodes (7nm, 5nm, or below) and FinFET technologies. Knowledge of machine learning or AI techniques for test optimization.