3439 Tcl Jobs - Page 16

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to ...

You will be part of ACE India , in the P- Core design team driving Intel's latest CPU's in the latest process technology. As a DFT engineer direct responsibilities of the role, but not limited to, working on various aspects of PCORE DFT including Spyglass DFT, RTL implementation, Verification, Scan, and ATPG. The candidate must be able to drive the DFT implementation for various features incl Scan, MBIST, TAP, etc. Previous experience working with manufacturing engineering, pattern delivery, and post-silicon support is a definite plus. Qualifications: Candidate must possess a Master's degree in Electronics or Computer Engineering with at least 7 or more years of experience or a bachelor's de...

Why Join QFAI? Join a passionate team, dedicated to making a difference. We are a close-knit team, with strong mission, vision and values that guide our day-to-day. Recognition of work, respect, and our multicultural community are key aspects of the employee experience and contribute to our continued success. Would you like to be part of our story? Don't hesitate, come and join us! About this opportunity We are seeking a highly skilled and passionate Formal Verification Engineer to join our team working with the best in the Industry, developing innovative ASIC solutions for data center and AI Infrastructure. The ideal candidate will develop comprehensive formal test plans and be responsible ...

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Enginee...

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Enginee...

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Enginee...

Designs, develops, and builds analog circuits in advanced process nodes for analog and mixedsignal IPs. Designs floorplans, performs circuit design, extracts chip parameters, and simulates analog behavior models. Creates test plans to verify design according to circuit and block microarchitecture specifications and evaluates test results. Verifies functionality to optimize circuit for power, performance, area, timing, and yield goals. Collaborates cross functionally to report design progress and collects, tracks, and resolves any performance and circuit design issues. Optimizes performance, power, area, and reduces leakage of circuits. Works with architecture and layout team to design circui...

Description Role Overview : We are looking for a highly experienced L3 Network Engineer to lead the design, implementation, and support of global IT infrastructure solutions. This role requires a deep understanding of networking, hosting (cloud and on-premise), endpoint security, and integration of enterprise systems. The successful candidate will serve as the final technical escalation point, drive infrastructure initiatives, and ensure security, scalability, and high availability across the landscape. Key Responsibilities Act as a senior technical authority, engaging with multiple domains and business units to translate demand into secure and scalable solutions. Define and implement cloud-...

As a Qualcomm Hardware Engineer at Qualcomm India Private Limited, you will play a crucial role in planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various other cutting-edge technologies to launch world-class products. You will collaborate with cross-functional teams to develop innovative solutions and meet performance requirements. Key Responsibilities: - Hands-on experience in different PnR steps including Floorplanning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post route optimization, ECO implementation, and DRC closure. - Proficiency in high frequency design & advanced tech node implement...

As a Senior Cache and Memory Design Engineer, you will be responsible for designing and developing memory subsystem solutions for the semiconductor portfolio. Working within the Cache and Memory Design Team, you will collaborate with highly skilled engineers from other teams to create efficient and high-performance memory subsystems critical for modern designs. Key Responsibilities: - Define address map, CHI and CXL protocols, cache, and bank memories - Utilize proficiency in RTL design using Verilog or VHDL - Apply knowledge of scripting languages such as Python, Perl, Bash, and TCL - Experience with Timing and Timings Constraints - Familiarity with revision control methodology and tools li...

As a Design Engineering Manager at Cadence, you will be responsible for leading pre-silicon Physical Layer Electrical Validation infrastructure development and post-silicon validation efforts, primarily focusing on Cadence's High-Speed SERDES Test chips. Your role will involve designing the hardware and software architecture required for testing the test chips, defining rigorous test plans, implementing tests, and generating high-quality test reports based on the results. In addition, you will have the opportunity to work on cutting-edge technology and be part of a diverse team dedicated to customer success and innovation. **Key Responsibilities:** - Lead pre-silicon Physical Layer Electrica...

1. Minimum of three years of hands-on Test Development experience (DFT, EDA tools, etc..) 2. Solid knowledge & experience in defining test solutions for multi-million gate SOC (Scan & MBIST) with Mixed Signal IPs (PLL, High Speed SERDES, DDR) 3. Knowledgeable in full SOC design and manufacturing cycle with specialized/direct experience in multiple areas; RTL/Custom Logic design, Synthesis, P&R, STA, Integration, Verification, Characterization and ATE test 4. Strong understanding of relationships between Hardware, Firmware and Software in FPGA and/or multi-processors SOC. Past experience in leading the team to successful silicon bring-up and problem solving in a complex system 5. Strong plann...

He/She should be able to do block level / top-level floor planning, PG Planning, partitioning (for hierarchical designs) , placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks and be able to fix the violations . S hould have worked on 4 5nm , 28nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. Provide technical guidance, mentoring to physical design eng inee rs. Interface with front-end ASIC teams to resolve issues. Excellent comm...

General Summary: Qualcomm is the world's leading developer of next generation of always on Display technologies and is committed to building a world-class organization that will lead the industry. Be part of the team developing next generation Display subsystems and Display peripherals. The ASIC Systems Architect is responsible for system architecture definition activities supporting a sophisticated multimedia Low Power Display subsystem catering to various market segments like mobile, XR, compute, IOT, Wearables and automotive products. Candidates will be responsible for all aspects of the ASIC hardware architecture definition/validation including the following: Owning end to end system arc...

Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. PD JD: Thorough knowledge of the ASIC designs Place and Route flow and methodology. Hands-on experience in executing complete PD ownership from netlist to GDS2 including HM level...

Key Responsibilities: Lead the architecture, design, and integration of SoC-wide clocking networks including clock generation (PLLs, DLLs), distribution, gating, and domain crossing strategies. Define and optimize power-performance-area (PPA) trade-offs for complex clocking and circuit topologies. Collaborate cross-functionally with RTL, physical design, verification, and DFT teams to deliver end-to-end SoC clocking and custom IP. Own the technical roadmap and methodology improvements for clocking, timing closure, and custom circuits. Mentor and technically guide a team of junior and senior designers. Review and approve specifications, schematics, simulations, and post-layout signoff for hig...

Roles and Responsibilities: Perform RTL-to-GDSII implementation including floorplanning, placement, clock tree synthesis (CTS), routing, and timing closure. Work on P&R flows using tools such as Cadence Innovus / Synopsys ICC2 . Handle timing analysis and sign-off using PrimeTime / Tempus . Perform power planning, IR-drop, and EM analysis to meet reliability targets. Execute DFM closure DRC/LVS/ANT checks using Calibre . Implement ECOs for timing, functionality, and metal fixes. Work closely with front-end, verification, and DFT teams to ensure full-chip integration and timing convergence. Optimize Power, Performance, and Area (PPA) for block- and top-level designs. Contribute to flow automa...

Responsible for high performance microprocessor blocks RTL to GDSII implementation Perform block level synthesis, floor-planning, placement and routing. Close the design to meet timing, power budget and area. Implement ECO's to address functional bugs and timing violations. Team player, with good problem solving and communication skills. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5-8 years industry experience in physical design methodology. Good knowledge and hands on experience in physical design methodology which include logic synthesis,placement, clock tree synthesis, routing . Should be knowledgeable in physical ...

Responsible for high performance microprocessor blocks RTL to GDSII implementation Perform block level synthesis, floor-planning, placement and routing. Close the design to meet timing, power budget and area. Implement ECO's to address functional bugs and timing violations. Team player, with good problem solving and communication skills. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8-10 years of industry experience in physical design methodology. Good knowledge and hands-on experience in physical design methodology, which includes logic synthesis, placement, clock tree synthesis, routing. Should be knowledgeable in phy...

Job Details: If you are a senior leader with expertise in Design for Test and are passionate about defining the future of Client and Hyperscaler designs and SoC's, Intel has opportunities for you.The Central Engineering group is responsible for delivering industry-leading Custom Silicon Solutions for Intel Customers in the Client and Hyperscaler Domains. The DFT Director's responsibilities include (but are not limited to): Lead the product DFT Architecture for the Intel Custom Silicon Business Drive DFT technical readiness (TR) and define DFT strategy to meet the Intel Manufacturing requirements Work with the team to define DFT quality control/process for SoC execution predictability and hig...

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and ...

7+ years of experience in ASIC/SoC Physical Design and STA implementation. Prior experience in handling complex hierarchical designs and leading block-level or top-level integration . Required Skills & Tools: Strong expertise in ASIC Physical Design flow (Synthesis to GDSII) . Hands-on experience with EDA tools such as: Synopsys : Design Compiler, ICC2, PrimeTime Cadence : Innovus, Tempus Mentor Graphics : Calibre In-depth understanding of STA concepts — setup/hold analysis, OCV/AOCV, SI, and Crosstalk. Knowledge of clock tree design , power optimization techniques , and floorplanning strategies . Familiarity with Scripting (TCL, Perl, Python, or Shell) for automation. Understanding of found...

Line of Service Advisory Industry/Sector FS X-Sector Specialism Risk Management Level Associate Job Description & Summary At PwC, our people in cybersecurity focus on protecting organisations from cyber threats through advanced technologies and strategies. They work to identify vulnerabilities, develop secure systems, and provide proactive solutions to safeguard sensitive data. As a cybersecurity generalist at PwC, you will focus on providing comprehensive security solutions and experience across various domains, maintaining the protection of client systems and data. You will apply a broad understanding of cybersecurity principles and practices to address diverse security challenges effectiv...

Job Details: Job Description: Directs and manages a team of physical design engineers responsible for the physical design implementation of a chip design, subsystem, or block including clocking, timing, and integration Provides guidance on physical design implementation and analyzes layout designs, power delivery, place, route, clock tree synthesis, and other aspects of physical design Manages development of complex layout integrated circuit designs, simulation designs, RTL to GDS, logic synthesis, and oversees documentation for SoC development Reviews circuit layouts architectures and prototypes, ensures issue resolution, and optimizes circuit output Oversees physical design verification fl...

Job Description: We are looking for a Lead STA (Static Timing Analysis) Engineer to join our semiconductor design team. The ideal candidate will have extensive experience in ASIC/SoC timing analysis, closure, and signoff , along with deep knowledge of industry-standard tools like PrimeTime or Tempus . You will be responsible for driving timing closure , ensuring robust design constraints, and collaborating with Physical Design, Synthesis, and Signoff teams to deliver high-performance silicon. Roles and Responsibilities: Perform Static Timing Analysis (STA) across multiple corners and modes (MMMC). Debug and resolve setup, hold, recovery, and removal violations. Own and maintain timing constr...