As a DFT Engineer, you will be responsible for developing and implementing Design for Test methodologies for complex VLSI designs. You will ensure the testability and manufacturability of our products by working closely with design, verification, and physical design teams, Responsibilities: Develop and implement DFT architectures and strategies for complex SoC designs. Insert and verify DFT features such as scan chains, Built-In Self-Test (BIST) for memory and logic, and boundary scan (IEEE 1149.1/1149.6). Perform ATPG (Automatic Test Pattern Generation) and analyze coverage metrics to ensure high fault coverage. Collaborate with RTL designers to ensure seamless integration of DFT features into the design. Debug and resolve test-related issues in simulation, silicon validation, and production. Work closely with the physical design team to implement scan and clock constraints for timing closure. Optimize test time, power, and cost without compromising coverage and quality. Participate in silicon bring-up and post-silicon validation activities. Generate and maintain DFT documentation, including test plans, methodologies, and results. Requirements: Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. 4 to 10 years of experience in DFT for VLSI designs. Strong knowledge of DFT methodologies, including ATPG/MBIST/Scan InsertionVerilog/ System Verilog and scripting languages (Python, TCL, Perl). Solid understanding of STA concepts and constraints related to DFT. Experience in debugging silicon and ATE test patterns. Excellent problem-solving skills and ability to work in a collaborative environment. Familiarity with fault diagnosis and yield improvement methodologies. Exposure to advanced nodes (7nm, 5nm, or below) and FinFET technologies. Knowledge of machine learning or AI techniques for test optimization.

As a DFT Engineer, you will be responsible for developing and implementing Design for Test methodologies for complex VLSI designs. You will ensure the testability and manufacturability of our products by working closely with design, verification, and physical design teams. Responsibilities: Develop and implement DFT architectures and strategies for complex SoC designs. Insert and verify DFT features such as scan chains, Built-In Self-Test (BIST) for memory and logic, and boundary scan (IEEE 1149.1/1149.6). Perform ATPG (Automatic Test Pattern Generation) and analyze coverage metrics to ensure high fault coverage. Collaborate with RTL designers to ensure seamless integration of DFT features into the design. Debug and resolve test-related issues in simulation, silicon validation, and production. Work closely with the physical design team to implement scan and clock constraints for timing closure. Optimize test time, power, and cost without compromising coverage and quality. Participate in silicon bring-up and post-silicon validation activities. Generate and maintain DFT documentation, including test plans, methodologies, and results. Requirements: Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. 4 to 10 years of experience in DFT for VLSI designs. Strong knowledge of DFT methodologies, including ATPG/MBIST/Scan Insertion Verilog/ System Verilog and scripting languages (Python, TCL, Perl). Solid understanding of STA concepts and constraints related to DFT. Experience in debugging silicon and ATE test patterns. Excellent problem-solving skills and ability to work in a collaborative environment. Familiarity with fault diagnosis and yield improvement methodologies. Exposure to advanced nodes (7nm, 5nm, or below) and FinFET technologies. Knowledge of machine learning or AI techniques for test optimization.

Join Our Aprisa Team! Looking for Siemens EDA ambassadors Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the Increasingly complex world of chip, board, and system design. We Make Real What Matters. This is your role. At Aprisa, we offer complete functionality for top-level hierarchical design and block-level implementation for complex digital IC designs. Our detail-route-centric architecture and hierarchical database enable you to accelerate design closure and achieve optimal quality of results at a driven runtime. We're excited to be working on the next-generation RTL-to-GDSII solution, and we want YOU to be a part of this innovative journey! This is the Role Drive and be responsible for the design and development of various pieces of the RTL synthesis technology, logic optimizations, RTL design IP development, and low power synthesis. Guide and lead others toward successful project completion by innovating and implementing powerful solutions. Collaborate with a hardworking team of experts. Must-Have Requirements B.Tech or M.Tech in CSE/EE/ECE from a reputed engineering college with 5-8 years of experience in software development. Validated understanding of C/C++, algorithms, and data structures. Demonstrate excellent problem-solving and analytical skills. Lead and encourage the team with your expertise. Great to Have Experience in: You will have the opportunity to develop RTL synthesis tools and work with System Verilog, VHDL, DFT, formal verification, and Dynamic Power. Additionally, you will design C or RTL IPs and optimize RTL & gate level logic, area, timing, and power. Your experience in developing parallel algorithms and job distribution strategies will be highly valued, as well as your proficiency in using scripting languages like Python and Tcl. We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Show more Show less

Job Details Job Description: You will be part of ACE India , in the P- Core design team driving Intel's latest CPU's in the latest process technology. In this position, you will be responsible for power delivery network design, IR Drop analysis and convergence of complex core design. Your Responsibilities Will Include But Not Limited To Responsible for power delivery network design including package/bump to device level delivery for over 5GHz Freq and low-power digital designs. Deep understanding of RV and IR Drop concepts. Load line definition Closely work with SD, Integration and Floor plan teams Qualifications You must possess a master's degree in electrical or Electronics Engineering with at least 6 or more years of experience in related field or a bachelor's degree with at least 8 years of experience. With a deep Technical Expertise On - power delivery network IR and RV analysis, MIM spread with Tools: Redhawk, RHSC Additional preferred Skills being. Technical Expertise in Static Timing Analysis is preferred. Preferred Additional Skills Experience of handle complex core design, high-speed designs Timing signoff flows/tools experience both/either Synopsys/Cadence tools Very good knowledge on Timing tools, flows and methodology Ability to handle new feature feasibility studies SD flow knowledge would be plus Familiarity with Verilog/VHDL Tcl, Perl, Python scripting Strong verbal and written communication skills Job Type Experienced Hire Shift Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. Show more Show less

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. We are looking for bright ASIC design engineers with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering Snapdragon CPU design, flows for high performance SoCs in sub-10nm process for Mobile, Compute and IOT market space. Job Responsibilities: Participate on a project involved in the development of ASICs, with emphasis in Place and Route Implementation, Timing Closure, Low Power, Power Analysis and Physical Verification. Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward Work closely with RTL design, Synthesis, low power, Thermal, Power analysis and Power estimation teams to optimize Performance, Power and Area(PPA) Tabulate metrics results for analysis comparison Develop Place & Route recipes for optimal PPA Minimum Qualifications 2+ years of High Performance core Place & Route and ASIC design Implementation work experience Preferred Qualifications Minimum 3+ years of experience in PD Extensive experience in Place & Route with FC or Innovus is an absolute must Complete ASIC flow with low power, performance and area optimization techniques Experience with STA using Primetime and/or Tempus is required Proficient in constraint generation and validation Experience of multiple power domain implementation with complex UPF/CPF definition required Formal verification experience (Formality/Conformal) Perl/Tcl, Python, C++ skills are needed Strong problem solving and ASIC development/debugging skills Experience with CPU micro-architecture and their critical path Low power implementation techniques experience High speed CPU implementation Clock Tree Implementation Techniques for High Speed Design Implementation are required Exposure to Constraint management tool and Verilog coding experience Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3069944 Show more Show less

Join Our Aprisa Team! Looking for Siemens EDA ambassadors Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the Increasingly complex world of chip, board, and system design. We Make Real What Matters. This is your role. At Aprisa, we offer complete functionality for top-level hierarchical design and block-level implementation for complex digital IC designs. Our detail-route-centric architecture and hierarchical database enable you to accelerate design closure and achieve optimal quality of results at a driven runtime. We're excited to be working on the next-generation RTL-to-GDSII solution, and we want YOU to be a part of this innovative journey! This is the Role Drive and be responsible for the design and development of various pieces of the RTL synthesis technology, logic optimizations, RTL design IP development, and low power synthesis. Guide and lead others toward successful project completion by innovating and implementing powerful solutions. Collaborate with a hardworking team of experts. Must-Have Requirements B.Tech or M.Tech in CSE/EE/ECE from a reputed engineering college with 5- 8 years of experience in software development. Validated understanding of C/C++, algorithms, and data structures. Demonstrate excellent problem-solving and analytical skills. Lead and encourage the team with your expertise. Great to Have Experience in: You will have the opportunity to develop RTL synthesis tools and work with System Verilog, VHDL, DFT, formal verification, and Dynamic Power. Additionally, you will design C or RTL IPs and optimize RTL & gate level logic, area, timing, and power. Your experience in developing parallel algorithms and job distribution strategies will be highly valued, as well as your proficiency in using scripting languages like Python and TCL. We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Show more Show less

Job Summary:-_ Seeking highly motivated, energetic, team-oriented Individual Contributor driving roadmaps for IP / SS domain including complete IP portfolio, going deeper into logic design and architecting and developing Complex IPs / Subsystems solutions. Working closely with experienced and motivated team of Global experts in Systems, SoC Design functions to address the design/architectural challenges in the context of the complex IP and overall System level solutions. Work through a wide spectrum of skill from developing High level Specifications to actual design Implementation. Key Responsibilities: Own and drive Roadmaps for complete IP / Subsystem domains portfolio within global R&D team. Perform benchmarks against other industry players and ensure differentiating features for our customer with high level of innovation. Architect and Design complex IP and Subsystems across a range of protocols required for Automotive Self Driving Vehicles (ADAS) both Vision and Radar, In-Vehicle networks, Gateway Systems, Fail Safe Subsystems (ASIL-D) etc. Own and Lead IP / Subsystem from Concept till IP Design and Development achieving final design performance in integrated system within aggressive, market driven schedules. Ensure quality adherence during all stages of the IP development cycle and carry out a thorough analysis of existing processes, recommend and implement the process improvements to ensure ‘Zero Defect’ designs and drive and mentor teams towards that. Key Skills Self starter with 10-14 years of hands-on experience to Architect and Design complex IP design / Sub-system with minimal supervision. Custom Processor Designs with key DSP functions like those needed for Vision and Radar processing. Experience in High Speed Serial protocols and associated high speed challenges on controller and PHY for PCIe, Ethernet & MIPI CSI2. Understanding of key External Memory interface protocols including DDR4 / LPDDR4, QuadSPI Flash interfaces. Experience in microcontroller architecture, Cache, protocols like AHB/AMBA,AXI. Extensive hands on knowledge of HDLs (Verilog/VHDL), Scripting languages (Perl, Tcl), C/C++ for hardware modeling. Understanding of end to end IP development flow including complex CDC, RDC constructs, IP Synthesis, DFT ATPG coverage. Have worked on Testbench and Testplan development closely with the verification team. Hands on work on pre silicon validation using FPGA/Emulation Board would be a significant added advantage. Key Soft Skills Proficient skills in both written and verbal communication. Can articulate well. Has a sense of Ownership and engages everyone with Trust and Respect. Should demonstrate Emotional Intelligence and Leadership values with ability to work well as a part of team both local and remote or multisite Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and skilled ASIC Digital Design Engineer with a strong foundation in both analog and digital CMOS circuit designs. You thrive in dynamic environments and are adept at working with Verilog/System Verilog languages and methodologies such as VMM and UVM. You have a knack for writing and modifying test cases, checkers, and scoreboards within a system Verilog-based test environment. Your expertise extends to AMS verification, particularly in high-speed SerDes designs supporting multi-protocols. Familiarity with Synopsys analog mixed-signal design tools and modeling languages like Verilog-A/AMS is a plus. You are proficient in programming/scripting languages like TCL, Perl, and Python, and have experience working with Linux. Your excellent communication skills and ability to take ownership of projects ensure that you meet deadlines and exceed expectations. Self-organization is second nature to you, allowing you to manage time effectively and contribute meaningfully to your team's success. What You’ll Be Doing: Defining and developing ASIC RTL design and verification at both chip and block levels. Writing and modifying test cases, checkers, and scoreboards in a system Verilog-based test environment. Collaborating with cross-functional teams to ensure seamless integration of analog and digital components. Conducting AMS verification, particularly for high-speed SerDes designs supporting multi-protocols. Utilizing Synopsys analog mixed-signal design tools for efficient design and verification processes. Programming and scripting using TCL, Perl, and Python to automate and streamline workflows. The Impact You Will Have: Enhancing the performance and reliability of our high-performance silicon chips. Contributing to the development of innovative technologies that drive the Era of Pervasive Intelligence. Improving the efficiency and effectiveness of our design and verification processes. Ensuring the seamless integration of analog and digital components in our products. Supporting the creation of cutting-edge solutions for self-driving cars, learning machines, and more. Driving continuous technological innovation within Synopsys and the broader industry. What You’ll Need: Looking for 2+yrs experience with BTech / MTech in VLSI / Electronics/ Microelectronics Knowledge or hands-on expertise/analysis of Analog and digital CMOS circuit designs Knowledge on electrical circuit networks and analysis Knowledge or hands-on Verilog/System Verilog languages and supported methodologies like VMM, UVM Must be able write/modify testcases, checkers, scoreboards in a system Verilog based test environment AMS verification experience in high speed Serdes designs supporting multi-protocols is an advantage. Experience with the Synopsys Analog mixed-signal design tool set is an advantage. Modelling languages Verilog-a/ams can be an advantage Programming/scripting know-how e. g. tcl, perl, python Experience with Linux Good communication skills, ability to take ownership Self-organized to ensure that project timescales are met Who You Are: Excellent communicator with strong interpersonal skills. Proactive and able to take ownership of projects. Self-organized and capable of managing time effectively. Collaborative team player who thrives in a dynamic environment. Detail-oriented and committed to delivering high-quality results. The Team You’ll Be A Part Of: You will join a dynamic team of engineers focused on pushing the boundaries of ASIC digital design and verification. Our team values collaboration, innovation, and continuous improvement, working together to create cutting-edge solutions that drive the future of technology. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

Job Opportunity: Seeking highly motivated, energetic, team-oriented person driving roadmaps for IP / Subsystem domain including complete IP portfolio, going deeper into logic design and architecting and developing Complex IPs / Subsystems solutions. Working closely with experienced and motivated team of Global experts in Systems, SoC Design functions to lead or address the design/architectural challenges in the context of the complex IP and overall System level solutions. Work through a wide spectrum of skill from developing High level Specifications to actual design Implementation. Key Responsibilities Own and drive Roadmaps for complete IP / Subsystem domains portfolio within global R&D team. Perform benchmarks against other industry players and ensure differentiating features for our customer with high level of innovation. Architect and Design complex IP and Subsystems across a range of protocols required for Edge processing and Automotive Self Driving Vehicles, In-Vehicle experience, Gateway Systems, Fail Safe Subsystems (ASIL-D) etc. Own, Lead an Drive IP / Subsystem from Concept till IP Design and Development achieving final design performance in integrated system within aggressive, market driven schedules. Ensure quality adherence during all stages of the IP development cycle and carry out a thorough analysis of existing processes, recommend and implement the process improvements to ensure ‘Zero Defect’ designs and drive and mentor teams towards that. Own and Drive global IP design methodologies across sites with global stakeholders. Key Skills Self starter with 18+ years of experience to Architect and Design complex IP design / Sub-system with minimal supervision. Custom Processor Designs with key DSP functions like those needed for Vision and Radar processing, Processor Designs like RISC-V Core, Cache based subsystems. Experience in High Speed Serial protocols and associated high speed challenges on controller and PHY for PCIe, Ethernet & MIPI CSI2. Understanding of key External Memory interface protocols including DDR4 / LPDDR4, QuadSPI Flash interfaces. Experience in microcontroller architecture, bus protocols like AHB/AMBA,AXI. Extensive hands on knowledge of HDLs (Verilog/VHDL), Scripting languages (Perl, Tcl), C/C++ for hardware modeling. Understanding of end to end IP development flow including complex CDC, RDC constructs, IP Synthesis, DFT ATPG coverage. Have worked on Testbench and Testplan development closely with the verification team. Hands on work on pre silicon validation using FPGA/Emulation Board would be a significant added advantage. Key Soft Skills Proficient skills in both written and verbal communication. Can articulate well. Has a sense of Ownership and engages everyone with Trust and Respect. Should demonstrate Emotional Intelligence and Leadership values with ability to work well as a part of team both local and remote or multisite. More information about NXP in India... Show more Show less

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 2-10 yrs experience in Physical Design and timing signoff for high speed cores. Should have good exposure to high frequency design convergence for physical design with PPA targets and PDN methodology. Masters/Bachelors Degree in Electrical/Electronics science engineering with at least 2+ years of experience in IC design. Experience in leading block level or chip level Physical Design, STA and PDN activities. Work independently in the areas of RTL to GDSII implementation. Ability to collaborate and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Knowledge of low power flow (power gating, multi-Vt flow, power supply management etc.) Circuit level comprehension of time critical paths in the design Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.) Tcl/Perl scripting Willing to handle technical deliveries with a small team of engineers. Strong problem-solving skills. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3071173 Show more Show less

o Job Description: Experience: 4-6years Tapeout experience in block level PnR implementation including synthesis for medium to complex blocks o Good to have experience in TSMC/Intel lower technology node(16/14nm or below) o Experience in independently analyzing/resolving congestion, timing issues and basic understanding of clock tree build o Basic Timing understanding to independently analyze timing paths o Experience in ICC2/Innovus/DC tools, Fusion compiler being added advantage o Basic equivalency check understanding. Good to have Conformal LEC experience. o Should have understanding of basic shell scripting, tool based TCL scripting to automate redundant tasks Show more Show less

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Custom Compute and Storage (CCS) Business Unit closely collaborates with strategic customers in the development of advanced and highly complex SoCs, from architecture and design all the way through layout, packaging, prototype validation and production ramp up. The Emulation Center of Excellence (CoE) team is key part of this group, with global ownership and responsibility for delivering emulation infrastructure, validating the design on emulation and drive left shift of SW and post-silicon readiness for all of CCS products. As part of the Emulation CoE leadership, you will drive the emulation strategy, vendor platform enablement, testplan execution for a high quality design tape-out What You Can Expect Build and Lead a strong technical team of emulation experts to define emulation strategy and platform requirements, develop emulation testplan, and drive execution of the emulation verification for large CCS products on emulation platform such as Veloce, Zebu and Palladium. Work with various stakeholders to define the emulation HW requirements for CCS products, including platforms, hardware/software collaterals, transactors, speed-bridges etc. Work closely with emulation hardware vendor application engineers (AEs) to keep the emulation hardware, software ecosystem updated, drive debug and resolution of issues with the vendor and design team. Define and develop new capabilities HW/SW tools to enable acceleration of RTL and improve emulation/FPGA model usability for pre-Silicon and post-Silicon functional validation as well as SW development/validation Interface with and provide guidance to pre-silicon Validation teams for optimizing pre-Si validation environments, test suites and methodologies for emulation efficiency Develop and apply automation aids, flows and scripts in support of emulation ease of use and improvement of equipment utilization. What We're Looking For Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 10+ years of experience. Proven track record of managing technical teams and leading cross-functional teams for design emulation and verification. Substantial knowledge of emulation platforms offerings from various vendors such as Synopsys, Cadence, Siemens including extensive experience in building complex SOC emulation models Working knowledge in one or more of the following: Processor architecture, SOC components, SOC inter-connect buses, IO protocols (PCIe, CXL, Ethernet) and memory technologies interfaces (DDR, HBM) Strong understanding of product development process of large SOCs and verification/debug experience in emulation platforms. Strong experience in coding in scripting languages like Perl, Python, Tcl & UNIX Shell etc Additional Compensation And Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Show more Show less

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Custom Compute and Storage (CCS) Business Unit closely collaborates with strategic customers in the development of advanced and highly complex SoCs, from architecture and design all the way through layout, packaging, prototype validation and production ramp up. The Emulation Center of Excellence (CoE) team is key part of this group, with global ownership and responsibility for delivering emulation infrastructure, validating the design on emulation and drive left shift of SW and post-silicon readiness for all of CCS products. As part of the Emulation CoE leadership, you will drive the emulation strategy, vendor platform enablement, testplan execution for a high quality design tape-out What You Can Expect Build and Lead a strong technical team of emulation experts to define emulation strategy and platform requirements, develop emulation testplan, and drive execution of the emulation verification for large CCS products on emulation platform such as Veloce, Zebu and Palladium. Work with various stakeholders to define the emulation HW requirements for CCS products, including platforms, hardware/software collaterals, transactors, speed-bridges etc. Work closely with emulation hardware vendor application engineers (AEs) to keep the emulation hardware, software ecosystem updated, drive debug and resolution of issues with the vendor and design team. Define and develop new capabilities HW/SW tools to enable acceleration of RTL and improve emulation/FPGA model usability for pre-Silicon and post-Silicon functional validation as well as SW development/validation Interface with and provide guidance to pre-silicon Validation teams for optimizing pre-Si validation environments, test suites and methodologies for emulation efficiency Develop and apply automation aids, flows and scripts in support of emulation ease of use and improvement of equipment utilization. What We're Looking For Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 10+ years of experience. Proven track record of managing technical teams and leading cross-functional teams for design emulation and verification. Substantial knowledge of emulation platforms offerings from various vendors such as Synopsys, Cadence, Siemens including extensive experience in building complex SOC emulation models Working knowledge in one or more of the following: Processor architecture, SOC components, SOC inter-connect buses, IO protocols (PCIe, CXL, Ethernet) and memory technologies interfaces (DDR, HBM) Strong understanding of product development process of large SOCs and verification/debug experience in emulation platforms. Strong experience in coding in scripting languages like Perl, Python, Tcl & UNIX Shell etc Additional Compensation And Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Show more Show less

Mirafra is hiring for Accelerated Verification Lead Job Description Results-driven and technically proficient Accelerated Verification Lead with over 13+ years ofexperience in SoC/IP functional verification, including more than 7 years focused on Accelerated verification on emulator, acceleration, and prototyping flows for automotive hardware designs. Proven expertise in leading cross-functional verification teams and developing reusable, accelerable UVM environments that seamlessly bridge simulation to emulation and post-silicon validation. Specialized in driving Verification and Validation (V&V) reuse strategies, enabling coverage continuity, testbench portability, and early software validation through hybrid verification frameworks. Deep experience in ISO 26262-compliant design verification, functional safety requirements, and integration of real-world automotive scenarios into pre-silicon validation. Proficient with Synopsys ZeBu, Siemens Veloce platforms, ensuring accelerated bring-up of SoCuse cases and reducing time-to-market. Adept in scripting and automation using Python, TCL, and Perl, with hands-on CI/CD, coverage analysis, and debug tools (SimVision, Verdi, Indago). Summary & Achievements• • Reduced post-silicon bug escapes through early software-driven validation in emulation environments. (Accelerated Verification)• • Cut SoC bring-up time by 50% by architecting a unified simulation-to-emulation testbench with reusable transactors. • • Spearheaded the Accelerated verification plan for a next-gen ADAS SoC including use cases like Start Up, BOOTROM, Complex data path , Negative tests• • Enabled 80% reuse of verification components across simulation, emulation, and prototype platforms through modular UVM design. • • Successfully led a AV verification team of engineers across DV, emulation Key Skills- Accelerated Verification: Synopsys Zebu, Siemens Veloce, Verification Methodologies: UVM, System Verilog, Accelerable UVM, C based V&V Reuse & Bridging: ** Simulation-to-Emulation Flow, Coverage Continuity, Transactor Development is desirable **Automotive Domain Knowledge: ** ISO 26262, Functional Safety, ADAS SoCs, CAN, LIN, Ethernet etc Power measurement with fsdb dump from Emulation environment. Regards Kalpana Bhatia TA-Lead -Mirafra kalpanabhatia@mirafra.com 9718012760 Show more Show less

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Data Center Engineering Business Unit closely collaborates with strategic customers in the development of advanced and highly complex SoCs, from architecture and design all the way through layout, packaging, prototype validation and production ramp up. This group provides technology development, EDA/methodology development and IP/Chip design development. India DFT team is a key part of Global DFT community with global ownership and responsibility for delivering generic and more advanced custom DFT architecture solutions, methodology and design. You will be working with this team to directly enable customer DFT requirements for Custom and Compute Businesses. What You Can Expect The position will be responsible for Architecting, Leading and implementing DFT / Test on complex IP and SOC for multiple Custom/Compute ASIC/SoC designs The execution involves Design-for-Test Architecture definition, Implementation of various DFT/DFX features, Validation , IP-DFT, STA, pattern generation & Post-Silicon Bringup and Debug for various designs/IPs in Custom/Compute space. In this position, the responsibility also includes mentoring, guiding and driving a small team of engineers enabling them for scaling across multiple designs. The position also involves definition and enhancement of DFT methodologies and tools to be able to benchmark them and enable new methodologies in the domain of DFT/Test. What We're Looking For Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience. Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 13+ years of experience. Hands on working experience in various stages of DFT-Execution SCAN-Insertion/MBIST/ATPG/Validation/STA/IP-DFX/Post-Silicon Bringup/Debug Thorough knowledge on various DFT/Test architecture solutions and should be involved in DFT-Architecture definition of at-least couple of Designs. Strong fundamentals in Digital Circuit Design and Logic Design is required Understanding of DFT Flows and Methodologies and Experience with Cadence/Mentor/Synopsys Tool set (Genus,Modus,NCSim / DC,Tessent,Spyglass/Tmax) Prior experience in ASIC design is a plus Scripting skills using PERL, Tcl and C-Shell is plus Additional Compensation And Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Show more Show less

Location Karnataka Bengaluru Experience Range 8 - 12 Years Job Description PD: Technical Skills: Should be able to handle Full chip PnR (timing/congestion/CTS issues), understanding of IO ring, package support, multi voltage design Deep understanding of the concepts related to synthesis, place & route, CTS, timing convergence, IR/EM checks and signoff DRC/LVS closure Responsible for independent planning and execution of all aspects of physical design including floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM Must have participated in all stages of the design (floor planning, placement, CTS, routing, physical verification, IREM) Well versed with the timing closure (STA), timing closure methodologies Good Understanding of DRC, LVS,ERC and PERC rule files for lower tech node layout verification Experience in lower tech node (<7nm) Good automation skills in PERL, TCL and EDA tool-specific scripting Able to take complete ownership for Block/sub-system for complete execution cycle Out of box thinking to meet tighter PPA requirements Qualification: BE/BTECH/MTECH in EE/ECE with proven experience in ASIC Physical Design Detailed knowledge of EDA tools and flows, Fusion compiler based RTL2GDS flow is desired Experience – 11+

We are looking for dynamic and driven individuals to join our marketing team. As an On-Field Marketing Executive, you will be responsible for building visibility, promoting products, and developing relationships across dealers and markets. Responsibilities: Promote leading electronic brands (Samsung, Panasonic, Carrier, TCL, Amstrad) across retail and distribution channels Conduct regular market visits and field surveys Generate leads and assist the sales team Support execution of local marketing campaigns and brand activations Requirements: Good communication and interpersonal skills Energetic and self-motivated Own two-wheeler is a plus Freshers may apply Benefits: Competitive salary Incentive-based growth Long-term career opportunity Contact: 9764221385

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains– LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting Principal Duties And Responsibilities: Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications: 8+ years Hardware Engineering experience or related work experience. 6+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3075847 Show more Show less

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.PNR implementation for Qualcomm SoC's Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains– LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting Principal Duties And Responsibilities: Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications: 8+ years Hardware Engineering experience or related work experience. 6+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3075848 Show more Show less

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum Qualifications: Good hands-on experience on Floorplanning, PNR and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains– LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting Principal Duties And Responsibilities: Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes. Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc) Quick learner with good analytical and problem solving skills Qualifications: 3+ years Hardware Engineering experience or related work experience. 3+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3075846 Show more Show less

Applied Materials is the leader in materials engineering solutions to produce virtually every new chip and advanced display in the world. Our expertise in modifying materials at atomic levels and on an industrial scale enables customers to transform possibilities into reality. Our innovations make possible™ the technology shaping the future. To achieve this, we employ some of the best, brightest, and most talented people in the world who work together as part of a winning team. Key Responsibilities Expertise in PDK enablement and library validation/automation. Hands-on experience with LVS/Parasitic extraction/standard cell characterization flows and methodologies Design/System level experience with DTCO and PPA analysis Hands-on expertise in TCL, Python, make and shell scripting Broad understanding of system design (product architecture, packaging, SRAM, DRAM, etc.) is a plus Strong understanding of the RTL2GDS concepts and methodology and experience with Synopsys/Cadence physical design tools (Fusion Compiler/Innovus) Knowledge of standard cell architecture and design tradeoffs with respect to PPA Proactively identify and act on new trends or developments in future technology nodes Ability to implement solutions and troubleshoot complex problems with limited or no supervision in area of expertise Creative thinking and ability to look ahead and anticipating future technology innovations/issues Ability to collaborate with internal stakeholders, customers and vendors Collaborate/participate in discussions to solve interdisciplinary technical issues in a cross-functional team environment Mandatory - PDK, DRC, LVS, Python, Physical Design Functional Knowledge Demonstrates depth and/or breadth of expertise in own specialized discipline or field Business Expertise Interprets internal/external business challenges and recommends best practices to improve products, processes or services Leadership May lead functional teams or projects with moderate resource requirements, risk, and/or complexity Problem Solving Leads others to solve complex problems; uses sophisticated analytical thought to exercise judgment and identify innovative solutions Impact Impacts the achievement of customer, operational, project or service objectives; work is guided by functional policies Interpersonal Skills Communicates difficult concepts and negotiates with others to adopt a different point of view Qualifications Education: Master's Degree Skills Certifications: Languages: Years of Experience: 7 - 10 Years Work Experience: Additional Information Shift: Day (India) Travel: Yes, 10% of the Time Relocation Eligible: Yes Applied Materials is an Equal Opportunity Employer committed to diversity in the workplace. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law. Show more Show less

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. The candidate will have responsibilities to maintain/upgrade infrastructure/automation for RTL development and design-verification teams at multiple locations using multiple server farms, some in the Amazon and IBM clouds and some on-premise. The candidate will also have responsibilities in managing/monitoring regression trends, automating error/defect reporting, and supporting users in various server farms. The candidate will have responsibilities to maintain/upgrade infrastructure/automation for RTL development and design-verification teams at multiple locations using multiple server farms, some in the Amazon and IBM clouds and some on-premise. The candidate will also have responsibilities in managing/monitoring regression trends, automating error/defect reporting, and supporting users in various server farms. We’re looking for a candidate who has the following skillsets: Extensive knowledge of Perl and Python Knowledge of dependency-checking via make, SCons LSF or other batch-queuing system (e.g. Grid, PBS, Open Lava), and script integration Using REST API (e.g. Jenkins, Jira) from Perl, Python Migrating scripts, script-libraries to different Linux OS releases Knowledge of SQL, relational database engines like MariaDB or PSQL, and integration with Perl/Python Knowledge of web technologies: Basic Apache setup, PHP, Javascript/Jquery, RSS automation These Skillsets And Knowledge Would Also Be Desirable BS/MS - Electrical / Computer Engineering. At least 7 years of of relevant experience. Updating/debugging TCL code embedded in a variety of tools, such as simulator, waveform-viewer, formal verification, in-house interpreter, etc. Knowledge of Verilog, SystemVerilog testbenches; some familiarity with methodologies like OVM or UVM; incorporate DPI or PLI models Some IT knowledge: NFS, memory/CPU profiling, NIS/DNS/LDAP, SMTP, syslog, cron, etc Jenkins install/configuration/management Module-files and modulecmd to manage tools and tool-versions Cloud deployment/maintenance: Amazon Web Services, MS Azure, IBM Cloud Experience with revision control like git or GitHub The position is based in Austin/San Jose/Bangalore (India) We’re doing work that matters. Help us solve what others can’t. Show more Show less

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Title: Lead Product Validation Engineer Location: Bangalore Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day. Job Summary As PV engineer, this person will be responsible for product validation [quality engineering] owning validation from test plan creation, test automation to bug tracking, follow-up and closing summary. The ideal candidate is expected to have understanding of semiconductor verification flow. Job Responsibilities Focus on quality of physical validation tool Pegasus by analyzing on existing functionality/regressions for customer deliverables and report failures in bug tracking system. Maintain regression tests with regular test cycles and integrate customer test cases as part of regression suites. Working closely with PE and R&D to develop test plan of new features and methodology for testing coverage improvement. Experience And Technical Skills Required 4+ to 7 years' experience in developing and supporting physical verification activities. Have 3+ years of experience in VLSI back-end domain Be expert in layout and physical verification concepts (DRC/FILL/LVS/PERC) Have solid working experience with UNIX and skilled in shell/perl/tcl/python scripting language Good communication, strong solving skill and working as a team player Strong knowledge of Cadence Virtuoso is a big plus Qualifications BE/BTech/ME/MS/MTech in Electrical/Electronics Behavioral Skills Required Must possess strong written, verbal and presentation skills Ability to establish a close working relationship with both customer peers and management Explore what’s possible to get the job done, including creative use of unconventional solutions Work effectively across functions and geographies Push to raise the bar while always operating with integrity We’re doing work that matters. Help us solve what others can’t. Show more Show less

At Juniper, we believe the network is the single greatest vehicle for knowledge, understanding, and human advancement the world has ever known. To achieve real outcomes, we know that experience is the most important requirement for networking teams and the people they serve. Delivering an experience-first, AI-Native Network pivots on the creativity and commitment of our people. It requires a consistent and committed practice, something we call the Juniper Way. Position: Technical Support Engineer – Security Role: Customer Focused Technical Support (CFTS) Engineer –Security Products and Technologies Location: Bangalore The Technical Support Engineer reports into the Global Services (GS) division of Juniper Networks, specifically as part of a comprehensive Juniper Technical Assistance Center (JTAC). JTAC challenges the status quo to provide multi-tiered services to Juniper’s top-tier customers worldwide – customers who test the traditional bounds of what can be done. In order to do this, Juniper’s premier customers increasingly rely on experts like the Technical Support Engineer by purchasing advanced service contracts in order to gain access to dedicated teams of highly competent, technically astute and network aware senior engineers in an organization known as Customer Focused Technical Support (CFTS). In short – our most expert customers can’t do what they do without a designated team of senior engineers. And that’s you -- with in-depth product knowledge (switching, routing and/or security) and highly focused troubleshooting skills relevant to a customer’s particular network. To meet the challenge, you need extensive experience supporting large-scale networks; as well as broad product knowledge in anyone of routing, switching or security (firewalls) , SDN domains. Your ability to troubleshoot product problems; diagnose critical and complex network issues; and learn your customer’s infrastructure and technologies; are what bring you applause, success and thanks in the Support organization. In this position, your primary role is one of “break/fix”, where your mastery of in-depth diagnostics quickly brings network assets back online and heads off future problems. As one tool, you replicate customers’ problems in Juniper’s state-of-the-art lab environment to determine the root cause, verify a fix, and recommend a solution. Key Responsibilities : Become the dedicated focal technical support contact and handle high priority issues for a limited number of Advanced Services customers, on specific Juniper Networks Routing products ( SRX High end and Low end series , Virtual SRX ) Gain in-depth knowledge of the Juniper infrastructure and technologies that are present in assigned customer’s network profile; including their network topology, features, configurations, and service history, which results in faster resolution. Take ownership of high priority or sensitive customer issues, Isolate Juniper product issues at network/hardware/software level, ensure prompt service restoration and resolution to the customer’s satisfaction, by using a systematic problem-solving approach. Replicate customer environments and issues in lab and work closely with Juniper Engineering team in providing bug fixes on software issues reported by customer. Work closely with other Global Services(GS) teams to ensure knowledge share of the customer’s networks, issues and solutions. Keep GS management informed of all sensitive issues Provide necessary support to the Service Managers for high profile technical escalations , Involvement in conference calls and/or face to face customer account meetings to discuss technical escalations. Develop and maintain skills in his/her core products and technologies and highlight any need for training as the customers networks evolve. Work with various technical teams within Juniper Networks regarding new products and feature improvements for reliability, availability, and serviceability. Contribute to technical documentation (White Papers, FAQs, Solutions) for internal and/or external use. Develop a “Can-Do” attitude and suggest ways to improve the team performance and increase customer’s satisfaction. This is an individual contributor role. There can be rotational weekend coverages to support customers. Minimum Qualifications: The candidate will have achieved a level of higher education (Bachelor or master’s degree in electrical engineering, computer science or equivalent) Atleast 5 years of working experience in the networking domain, [e.g. 3] of these years of which would be spent supporting large IP networks Solid working experience in most of the following : IP Networking basics: TCP/IP, Subnetting, IP Packet flow, OSI layers Security Technologies : VPNs, IPSec, GRE, SSL/SSH , QoS, DES, 3DES, MD5, SHA, PKI , Various Denial of Service attacks, SYN flood , Replay attacks Concepts of Stateful packet inceptions, Application of Firewalls, access/perimeter control, vulnerability management and intrusion detection Other protocols: NAT , OSPF , BGP , Ethernet, 802.1q/p VLAN, BFD, STP, RSTP, ARP, LACP , High availability (Clustering) and Gateway redundancy protocols (VRRP) Working experience with traffic generators and network protocols analysis tools Strong problem-solving and troubleshooting skills, applicable to large and complex network scenarios Strong customer management and customer service skills Excellent communication and presentation skills Language skills: English (fluent – verbal and written), Diplomacy and good customer facing skills to understand and effectively address sensitive customer situations Preferred Qualifications: Candidates with experience and certifications in Juniper Products like MX, PTX, QFX, EX, SRX, Contrail will be given preference JNCIE/CCIE lab or other security product certified personnel would have a distinct advantage Working experience with Operating System architectures (•nix , FreeBSD) , Virtualization, Hardware (CPU, memory, controller (and so on types), Scripting languages (TCL, Perl, Ansible, Puppet, C , C++), Service daemons (DHCP, DNS, TACACS, Radius) Personal Traits: Customer Centric Team Player Problem-solving mindset Action attitude Other Information [regional specific]: Relocation is available for this position Travel requirements for the position less than 10% About Juniper Networks Juniper Networks is in the business of network innovation. From devices to data centers, from consumers to cloud providers, Juniper Networks delivers the software, silicon and systems that transform the experience and economics of networking. The company serves customers and partners worldwide. Additional information can be found at www.juniper.net Juniper is an Equal Opportunity workplace and Affirmative Action employer. We do not discriminate in employment decisions on the basis of race, colour, religion, gender (including pregnancy), national origin, political affiliation, sexual orientation, gender identity or expression, marital status, disability, genetic information, age, veteran status, or any other applicable legally protected characteristic. All employment decisions are made on the basis of individual qualifications, merit, and business need. About Juniper Networks Juniper Networks challenges the inherent complexity that comes with networking and security in the multicloud era. We do this with products, solutions and services that transform the way people connect, work and live. We simplify the process of transitioning to a secure and automated multicloud environment to enable secure, AI-driven networks that connect the world. Additional information can be found at Juniper Networks (www.juniper.net) or connect with Juniper on Twitter, LinkedIn and Facebook. WHERE WILL YOU DO YOUR BEST WORK? Wherever you are in the world, whether it's downtown Sunnyvale or London, Westford or Bengaluru, Juniper is a place that was founded on disruptive thinking - where colleague innovation is not only valued, but expected. We believe that the great task of delivering a new network for the next decade is delivered through the creativity and commitment of our people. The Juniper Way is the commitment to all our colleagues that the culture and company inspire their best work-their life's work. At Juniper we believe this is more than a job - it's an opportunity to help change the world. At Juniper Networks, we are committed to elevating talent by creating a trust-based environment where we can all thrive together. If you think you have what it takes, but do not necessarily check every single box, please consider applying. We’d love to speak with you. Additional Information for United States jobs: ELIGIBILITY TO WORK AND E-VERIFY In compliance with federal law, all persons hired will be required to verify identity and eligibility to work in the United States and to complete the required employment eligibility verification form upon hire. Juniper Networks participates in the E-Verify program. E-Verify is an Internet-based system operated by the Department of Homeland Security (DHS) in partnership with the Social Security Administration (SSA) that allows participating employers to electronically verify the employment eligibility of new hires and the validity of their Social Security Numbers. Information for applicants about E-Verify / E-Verify Información en español: This Company Participates in E-Verify / Este Empleador Participa en E-Verify Immigrant and Employee Rights Section (IER) - The Right to Work / El Derecho a Trabajar E-Verify® is a registered trademark of the U.S. Department of Homeland Security. Juniper is an Equal Opportunity workplace. We do not discriminate in employment decisions on the basis of race, color, religion, gender (including pregnancy), national origin, political affiliation, sexual orientation, gender identity or expression, marital status, disability, genetic information, age, veteran status, or any other applicable legally protected characteristic. All employment decisions are made on the basis of individual qualifications, merit, and business need. Show more Show less

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. This opportunity is for a Principal Product Engineer in the Digital and Signoff Group (DSG) at Cadence. The Cadence Digital and Signoff Group will offer you a dynamic environment in which you will work with innovative R&D and Customer Engagement teams to influence the development of software tools for advanced chip design platforms. As a Principal Product Engineer for Liberate, you will engineer innovative and quality characterization solutions/methods for foundational IPs, working closely with R&D and fellow engineers. You will work on customer activities, run competitive benchmarks, develop flows and solutions to proliferate our technologies at customers. You will also work very closely with customers to drive product adoptions and campaigns, as well as drive partnership and collaborative projects with customers. Experience And Technical Skills Required Foundational IP characterization expertise, and Liberty modeling expertise. Deep understanding of different Liberty formats: NLDM, CCS, ECSM, LVF, EM, Aging etc. Firsthand experience performing characterizations with an industry-standard solution. Firsthand experience with industry-standard circuit simulators. Good understanding of integrated circuit operation and CMOS fundamentals. Fair understanding of process variation, and statistical characterization, with familiarity at advanced process nodes (5nm, 3nm etc.) Coherent problem-solving skills to debug customer problems and propose solutions. Automation skills using Tcl, Python, and shell scripting. Experience with Memory or Macro or Mixed-Signal characterization is a plus. Experience with Cadence Liberate is a plus. Experience with Cadence Spectre is a plus. Qualifications BE/BTech/ME/MS/MTech or equivalent We’re doing work that matters. Help us solve what others can’t. Show more Show less